topic Re: ECC Sram test in S32K

ECC Sram test

smt87 — Thu, 28 Jul 2022 06:11:06 GMT

Hi,

I am using S32K11x MCU for my project. I am using ECC reporting for safety mechanism, so I did initializations as follows. Do you have any idea how i can check this sample function working correctly?

ERM->SR0 = ERM_SR0_SBC0_MASK | ERM_SR0_NCE0_MASK

ERM->CR0 = ERM_CR0_ESCIE0_MASK | ERM_CR0_ENCIE0_MASK

EIM->EICHDn[0].WORD0 = 0x00000000; /* CHKBIT[31-25] remain unmodified */
EIM->EICHDn[0].WORD1 = 0x00000003;

EIM->EICHEN |= EIM_EICHEN_EICH0EN_MASK; /* Error Injection Channel 0 Enable (SRAM_L)*/
EIM->EIMCR |= EIM_EIMCR_GEIEN_MASK; /* Global Error Injection Enable */

Re: ECC Sram test

davidtosenovjan — Fri, 29 Jul 2022 13:02:13 GMT

Here you may find example code:

https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K14x-SRAM-ECC-Injection/ta-p/1129181

Re: ECC Sram test

smt87 — Mon, 01 Aug 2022 06:29:51 GMT

Hi,

I used this code. But I am using S32K116 and after the following code is run, system is generating error. What is the problem here? What can i do to solve this?

/* ERM_SR */
ERM->SR0 |= ERM_SR0_SBC0(1U) | /* w1c SRAM_L Single-Bit Correction flag */
ERM_SR0_NCE0(1U); /* w1c SRAM_L Non-Correctable Error flag */

/* ERM_CR */
ERM->CR0 |= ERM_CR0_ESCIE0(1U) | /* Enable SRAM_L Single Correction Interrupt Notification */
ERM_CR0_ENCIE0(1U); /* Enable SRAM_L Non-Correctable Interrupt Notification */

/* Write the EICHDn_WORD registers before executing the two-stage-enable mechanism */
/* A write to any of this field clears the corresponding EICHEN[EICHnEN] enable bits */

/* SRAM_L */
EIM->EICHDn[0].WORD0 = 0x00000000; /* CHKBIT[31-25] remain unmodified */
EIM->EICHDn[0].WORD1 = 0x00000003; /* B0_3DATA_MASK[0-1] bits of the read data bus are inverted */

/* enable interrupts at core level */
Nvic::setPriority(ERM_fault_IRQn, system::ERM_IRQ_PRIO);
Nvic::enableInterrupt(ERM_fault_IRQn);

EIM->EICHEN |= EIM_EICHEN_EICH0EN(1U); /* Error Injection Channel 0 Enable (SRAM_L)*/

EIM->EIMCR |= EIM_EIMCR_GEIEN(1U); /* Global Error Injection Enable */
(void)EIM->EIMCR; /* Read-after_write */

Re: ECC Sram test

davidtosenovjan — Tue, 02 Aug 2022 07:31:05 GMT

Intention of ECC error injection is to generated error response or what you actually want to achieve?

Re: ECC Sram test

smt87 — Tue, 02 Aug 2022 07:36:57 GMT

Hi,

Actually this code is not wroking. I have one question that are these initialized codes true for S32k116?