https://community.nxp.com/t5/S32K/S32K344-MCAL-DEMO-issue/m-p/1497889#M16732 <P><SPAN>The S32K344 MCAL DEMO project based on EB Tresos Tool Built, the debug problem as below. </SPAN></P><P><SPAN>These bits cannot be set '1' that Mode Update Register is not finished in the MC_ME after Mcu_SetMode() be run.</SPAN></P><P><SPAN>the debugging window as below</SPAN></P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="lzh_0-1659082338382.jpeg" style="width: 671px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/188429i3B790EC8198C4D75/image-dimensions/671x461?v=v2" width="671" height="461" role="button" title="lzh_0-1659082338382.jpeg" alt="lzh_0-1659082338382.jpeg" /><span class="lia-inline-image-caption" onclick="event.preventDefault();">lzh_0-1659082338382.jpeg</span></span></P><P>checked all status of CGM\PLL\FXOSC, they are same as demand, refer to the window below</P><P>1. MC_CGM</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="lzh_1-1659083103405.jpeg" style="width: 677px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/188431i171B9785730D3400/image-dimensions/677x438?v=v2" width="677" height="438" role="button" title="lzh_1-1659083103405.jpeg" alt="lzh_1-1659083103405.jpeg" /><span class="lia-inline-image-caption" onclick="event.preventDefault();">lzh_1-1659083103405.jpeg</span></span></P><P><SPAN>2. PLL</SPAN></P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="lzh_2-1659083159490.jpeg" style="width: 678px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/188432i18B45F796EF91563/image-dimensions/678x179?v=v2" width="678" height="179" role="button" title="lzh_2-1659083159490.jpeg" alt="lzh_2-1659083159490.jpeg" /><span class="lia-inline-image-caption" onclick="event.preventDefault();">lzh_2-1659083159490.jpeg</span></span></P><P><SPAN>3. FXOSC</SPAN></P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="lzh_3-1659083226285.jpeg" style="width: 686px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/188433i284376742C43048E/image-dimensions/686x119?v=v2" width="686" height="119" role="button" title="lzh_3-1659083226285.jpeg" alt="lzh_3-1659083226285.jpeg" /><span class="lia-inline-image-caption" onclick="event.preventDefault();">lzh_3-1659083226285.jpeg</span></span></P> Fri, 29 Jul 2022 08:32:39 GMT lzh 2022-07-29T08:32:39Z https://community.nxp.com/t5/S32K/S32K344-MCAL-DEMO-issue/m-p/1497889#M16732 <P><SPAN>The S32K344 MCAL DEMO project based on EB Tresos Tool Built, the debug problem as below. </SPAN></P><P><SPAN>These bits cannot be set '1' that Mode Update Register is not finished in the MC_ME after Mcu_SetMode() be run.</SPAN></P><P><SPAN>the debugging window as below</SPAN></P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="lzh_0-1659082338382.jpeg" style="width: 671px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/188429i3B790EC8198C4D75/image-dimensions/671x461?v=v2" width="671" height="461" role="button" title="lzh_0-1659082338382.jpeg" alt="lzh_0-1659082338382.jpeg" /><span class="lia-inline-image-caption" onclick="event.preventDefault();">lzh_0-1659082338382.jpeg</span></span></P><P>checked all status of CGM\PLL\FXOSC, they are same as demand, refer to the window below</P><P>1. MC_CGM</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="lzh_1-1659083103405.jpeg" style="width: 677px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/188431i171B9785730D3400/image-dimensions/677x438?v=v2" width="677" height="438" role="button" title="lzh_1-1659083103405.jpeg" alt="lzh_1-1659083103405.jpeg" /><span class="lia-inline-image-caption" onclick="event.preventDefault();">lzh_1-1659083103405.jpeg</span></span></P><P><SPAN>2. PLL</SPAN></P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="lzh_2-1659083159490.jpeg" style="width: 678px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/188432i18B45F796EF91563/image-dimensions/678x179?v=v2" width="678" height="179" role="button" title="lzh_2-1659083159490.jpeg" alt="lzh_2-1659083159490.jpeg" /><span class="lia-inline-image-caption" onclick="event.preventDefault();">lzh_2-1659083159490.jpeg</span></span></P><P><SPAN>3. FXOSC</SPAN></P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="lzh_3-1659083226285.jpeg" style="width: 686px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/188433i284376742C43048E/image-dimensions/686x119?v=v2" width="686" height="119" role="button" title="lzh_3-1659083226285.jpeg" alt="lzh_3-1659083226285.jpeg" /><span class="lia-inline-image-caption" onclick="event.preventDefault();">lzh_3-1659083226285.jpeg</span></span></P> Fri, 29 Jul 2022 08:32:39 GMT https://community.nxp.com/t5/S32K/S32K344-MCAL-DEMO-issue/m-p/1497889#M16732 lzh 2022-07-29T08:32:39Z