https://community.nxp.com/t5/S32K/stack-underflow-and-overflow-control/m-p/1486763#M16271 <P>Hi,</P> <P>if a stack is placed at beginning/end of SRAM then you can get a hard fault as soon as the stack overflows/underflow.<BR />Or software can write a unique guard value to the SRAM area at the stack limit address. The software checks this address periodically. If guard value is overwritten, a stack overflow/underflow fault is reported by SW.</P> <P>BR, Petr</P> Fri, 08 Jul 2022 09:59:35 GMT PetrS 2022-07-08T09:59:35Z https://community.nxp.com/t5/S32K/stack-underflow-and-overflow-control/m-p/1485261#M16221 <P>Hi,</P><P>I want to control stack underflow and overflow. I use S32K116. I know it does not have DWT module. How can i control this safety controls in any way? What can i do for testing stack underflow?</P> Wed, 06 Jul 2022 09:25:05 GMT https://community.nxp.com/t5/S32K/stack-underflow-and-overflow-control/m-p/1485261#M16221 smt87 2022-07-06T09:25:05Z https://community.nxp.com/t5/S32K/stack-underflow-and-overflow-control/m-p/1486763#M16271 <P>Hi,</P> <P>if a stack is placed at beginning/end of SRAM then you can get a hard fault as soon as the stack overflows/underflow.<BR />Or software can write a unique guard value to the SRAM area at the stack limit address. The software checks this address periodically. If guard value is overwritten, a stack overflow/underflow fault is reported by SW.</P> <P>BR, Petr</P> Fri, 08 Jul 2022 09:59:35 GMT https://community.nxp.com/t5/S32K/stack-underflow-and-overflow-control/m-p/1486763#M16271 PetrS 2022-07-08T09:59:35Z