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    <title>topic ADC self calibration in S32K</title>
    <link>https://community.nxp.com/t5/S32K/ADC-self-calibration/m-p/1484079#M16185</link>
    <description>&lt;P&gt;Hi all,&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;We&amp;nbsp;are using S32K118 EVB and have the following doubts related to the ADC calibration:&lt;/SPAN&gt;&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;The&amp;nbsp;&lt;SPAN&gt;S32K1&lt;/SPAN&gt; reference manual says :&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; "The General Calibration Value Registers (CLPx) contain calibration information that is generated by the calibration function. These registers contain seven signed calibration values of varying widths in two's complement format".&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; We assume that those registers are CLPS, CLP0, CLP1, CLP2, CLP3, CLPX and&amp;nbsp;CLP9. But if we check the ADC calibration manual the valid CPLS values range is [30,120]. 120 is not in the range of a 7-bit signed number. Is it really signed?&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; 2. The ADC calibration manual says that CPLX and CLP9 are disabled for S32K, but after doing the calibration, these registers have different values than 0. Is it ok?&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thank you so much&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Mon, 04 Jul 2022 13:35:09 GMT</pubDate>
    <dc:creator>abpaz</dc:creator>
    <dc:date>2022-07-04T13:35:09Z</dc:date>
    <item>
      <title>ADC self calibration</title>
      <link>https://community.nxp.com/t5/S32K/ADC-self-calibration/m-p/1484079#M16185</link>
      <description>&lt;P&gt;Hi all,&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;We&amp;nbsp;are using S32K118 EVB and have the following doubts related to the ADC calibration:&lt;/SPAN&gt;&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;The&amp;nbsp;&lt;SPAN&gt;S32K1&lt;/SPAN&gt; reference manual says :&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; "The General Calibration Value Registers (CLPx) contain calibration information that is generated by the calibration function. These registers contain seven signed calibration values of varying widths in two's complement format".&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; We assume that those registers are CLPS, CLP0, CLP1, CLP2, CLP3, CLPX and&amp;nbsp;CLP9. But if we check the ADC calibration manual the valid CPLS values range is [30,120]. 120 is not in the range of a 7-bit signed number. Is it really signed?&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; 2. The ADC calibration manual says that CPLX and CLP9 are disabled for S32K, but after doing the calibration, these registers have different values than 0. Is it ok?&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thank you so much&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 04 Jul 2022 13:35:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/ADC-self-calibration/m-p/1484079#M16185</guid>
      <dc:creator>abpaz</dc:creator>
      <dc:date>2022-07-04T13:35:09Z</dc:date>
    </item>
    <item>
      <title>Re: ADC self calibration</title>
      <link>https://community.nxp.com/t5/S32K/ADC-self-calibration/m-p/1484330#M16198</link>
      <description>&lt;P&gt;Hi&amp;nbsp;abpaz,&lt;/P&gt;
&lt;P&gt;Can you tell me where to get &lt;STRONG&gt;ADC calibration manual&lt;/STRONG&gt;, so that I can check the difference between&amp;nbsp;&lt;STRONG&gt;S32K1 reference manual&lt;/STRONG&gt; and&amp;nbsp;&lt;STRONG&gt;ADC calibration manual&lt;/STRONG&gt;.&lt;/P&gt;
&lt;P&gt;Best Regards,&lt;BR /&gt;Robin&lt;/P&gt;</description>
      <pubDate>Tue, 05 Jul 2022 04:13:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/ADC-self-calibration/m-p/1484330#M16198</guid>
      <dc:creator>Robin_Shen</dc:creator>
      <dc:date>2022-07-05T04:13:12Z</dc:date>
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