topic Re: S32K146 LPSPI Example problem in S32K

S32K146 LPSPI Example problem

f_gaudon — Thu, 05 May 2022 09:08:33 GMT

Hi,

I've got some problems with the LSPSI example.

Before sending a SPI trame my TX and RX fifo counter are 0 .

After executing the ligne : LPSPI1->TDR = send; the RX counter has incremented to 1 but not the TX fifo counter ? Can someone explain me why ?

Besides that, I do not understand the ligne : LPSPI1->SR |= LPSPI_SR_TDF_MASK; /* Clear TDF flag */

Because in the RM, this bit seems not writable.

Thanks for your time and answers,

Florian

Re: S32K146 LPSPI Example problem

f_gaudon — Tue, 10 May 2022 09:14:20 GMT

I'm sending a SPI frame every second, the first start correctly but after few seconds, the RX fifo is full (nothing is connected on the SDIN pin) and the CS stay low after sending the last frame.

In the example, the flags cleared are in Read only mode, I still don't get it.

Re: S32K146 LPSPI Example problem

danielmartynek — Fri, 20 May 2022 11:26:07 GMT

Hi Florian,

The 16bit frame written to the TX FIFO goes to the TX shift register and is sent out. Meanwhile, an RX frame is received. That's why you see the frame in the RX FIFO but not in the TX FIFO.

If you don't want to read the RX data, you can set the RXMSK bit in the command (TCR)

Regarding the RDF, TDF clearing process, you are right, the example is not correct. The flags cannot be cleared by w1c.They get cleared automatically depending on the number of frames in the FIFOs and RXWATER / TXWATER thresholds.

BR, Daniel

Re: S32K146 LPSPI Example problem

f_gaudon — Mon, 23 May 2022 11:11:27 GMT

Hi Daniel,

Thanks for your answer, I understood I was receiving some frames on RX so I was reading them just to clear the RXFIFO. But the RXMSK bit you suggested seems to be a better option !

Thanks again

Florian