Double bit error detection in SRAM_L

Sankar_saba — Thu, 28 Apr 2022 05:30:52 GMT

I have enabled ERM->CR0[ESCIE0], ERM->CR0[ENCIE0], ERM->CR0[ESCIE1],ERM->CR0[ENCIE1] and corresponding register in S32k146 as per S32KReferenceManual. Using EIM,
injected Single bit error in SRAM_L, getting notification in ERM_single_fault_IRQHandler with ERM->SR0 as 0x80000000
injected Single bit error in SRAM_U, getting notification in ERM_single_fault_IRQHandler with ERM->SR0 as 0x40000000
injected Double bit error in SRAM_U, getting notification in ERM_double_fault_IRQHandler with ERM->SR0 as 0x04000000.
But while I inject Double bit error in SRAM_L, getting system reset. Not sure why reset in SRAM_U Double bit error injection.
My requirement is to capture both single bit & double bit error in SRAM and move the system to Safe state. is it feasible to implement?

topic Double bit error detection in SRAM_L in S32K

Double bit error detection in SRAM_L