topic can message mailbox filter in S32K

can message mailbox filter

AparnaSridharan — Tue, 05 Apr 2022 09:24:56 GMT

Hi,

I am following code which can accept all CAN ids. But I want to use message id from 0x200 to 0x210. Also whether these message id can be configured to single message buffer.

void FLEXCAN0_init(uint32_t RxID,uint32_t bps)
{
#define MSG_BUF_SIZE 4 /* Msg Buffer Size. (CAN 2.0AB: 2 hdr + 2 data= 4 words) */
uint32_t i = 0;

CAN0->RAMn[4 * MSG_BUF_SIZE + 0] = 0x04000000;

CAN0->RAMn[4 * MSG_BUF_SIZE + 1] = 0x4<<24;//RxID; /* Msg Buf 4, word 1: Standard ID = 0x111 */

/* PRIO = 0: CANFD not used */
CAN0->MCR = 0x0000001F;while ((CAN0->MCR && CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT) {
}

while ((CAN0->MCR && CAN_MCR_NOTRDY_MASK) >> CAN_MCR_NOTRDY_SHIFT) {
}

Re: can message mailbox filter

PetrS — Tue, 05 Apr 2022 19:06:47 GMT

Hi,

no, you cannot receive ID range 0x200-0x210 into single MB, you will need 2 MBs, one for ID range 0x200-0x20F and second for ID 0x210. Also you need to use individual masking registers, so have MCR[IMRQ] bit set. Then for example using MB3 and MB4 you can have

CAN0->RAMn[4 * MSG_BUF_SIZE + 1] = 0x200<<18; /* Msg Buf 4, word 1: Standard ID = 0x200 */
CAN0->RXIMR[4] = 0x3F0<<18; // mask for ID to dont care lower 4 bits, thus receive ID range 0x200-0x20F

CAN0->RAMn[3 * MSG_BUF_SIZE + 1] = 0x210<<18; /* Msg Buf 3, word 1: Standard ID = 0x210 */
CAN0->RXIMR[3] = 0x3FF<<18; // mask for exact match, thus receive ID 0x210

BR, Petr

Re: can message mailbox filter

AparnaSridharan — Wed, 06 Apr 2022 06:02:15 GMT

hi @PetrS ,

Whether any change need to be made with respect to RXMGMASK. Also when I make MCR[IMRQ] set the control stopped in default ISR.

To set that MCR[IMRQ] using this line

CAN0->MCR = 0x1 << 0xF;

Without setting this I changed the individual mask CAN0->RXIMR[4] as you have mentioned above. It accepts all message id.

For your reference below I have attached CAN initialization code,

void FLEXCAN0_init(uint32_t RxID,uint32_t bps)
{
#define MSG_BUF_SIZE 4 /* Msg Buffer Size. (CAN 2.0AB: 2 hdr + 2 data= 4 words) */
uint32_t i = 0;

PCC->PCCn[PCC_FlexCAN0_INDEX] |= PCC_PCCn_CGC_MASK; /* CGC=1: enable clock to FlexCAN0 */
CAN0->MCR |= CAN_MCR_MDIS_MASK; /* MDIS=1: Disable module before selecting clock */
CAN0->CTRL1 &= ~CAN_CTRL1_CLKSRC_MASK; /* CLKsrc=0: Clock Source = oscillator (8 MHz) */
CAN0->MCR &= ~CAN_MCR_MDIS_MASK; /* MDIS=0; Enable module config. (Sets FRZ, HALT)*/
while (!((CAN0->MCR & CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT)) {
}
uint32_t PRESDIV = 8000000 / (16*bps) -1;
/* Good practice: wait for FRZACK=1 on freeze mode entry/exit */
CAN0->CTRL1 = 0x00DB0006 | (PRESDIV<<24);
for (i = 0; i < 128; i++) { /* CAN[port]: clear 32 msg bufs x 4 words/msg buf = 128 words*/
CAN0->RAMn[i] = 0; /* Clear msg buf word */
}
//CAN0->MCR = 0x1 << 0xF;
for (i = 0; i < 16; i++) { /* In FRZ mode, init CAN[port] 16 msg buf filters */
CAN0->RXIMR[i] = 0xFFFFFFFF; //0xFFFFFFFF; /* Check all ID bits for incoming messages */
}
CAN0->RXIMR[4] = 0x3F0<<18;
//CAN0->RXIMR[4] = 0x3F0<<18;
CAN0->RXMGMASK =0x00000000;//x3F0<<18 ; /* Global acceptance mask: check all ID bits */

CAN0->RAMn[4 * MSG_BUF_SIZE + 0] = 0x4<<24;
CAN0->RAMn[4 * MSG_BUF_SIZE + 1] = 0x201<<18;//RxID; /* Msg Buf 4, word 1: Standard ID =*/

CAN0->MCR = 0x0000001F; /* Negate FlexCAN 1 halt state for 32 MBs */
while ((CAN0->MCR && CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT) {
}

while ((CAN0->MCR && CAN_MCR_NOTRDY_MASK) >> CAN_MCR_NOTRDY_SHIFT) {
}
}

Also this is my reciever code,

int FLEXCAN0_receive_msg( uint32_t RxID,uint32_t Rx_LENGTH, uint32_t Rx_DATA, uint32_t ACK )
/* Recieved message number of data bytes */
{ /* Receive msg from ID 0x501 using msg buffer 4 */
//CAN0-> IFLAG1 = 0x00000001;
int j;

/* If CAN 0 MB 4 flag is set (received msg), read MB4 */
RxCODE = (CAN0->RAMn[4 * MSG_BUF_SIZE + 0] & 0x07000000) >> 24; /* Read CODE field */
RxLENGTH = (CAN0->RAMn[4 * MSG_BUF_SIZE + 0] & CAN_WMBn_CS_DLC_MASK)>> CAN_WMBn_CS_DLC_SHIFT;
RxID = (CAN0->RAMn[4 * MSG_BUF_SIZE + 1] & CAN_WMBn_ID_ID_MASK)>> CAN_WMBn_ID_ID_SHIFT ;
for (j=0; j<2; j++) { /* Read two words of data (8 bytes) */
RxDATA[j] = CAN0->RAMn[ 4*MSG_BUF_SIZE + 2 + j];
}

RxTIMESTAMP = (CAN0->RAMn[0 * MSG_BUF_SIZE + 0] & 0x000FFFF);
CAN0->IFLAG1 = 0x00000010; /* Clear CAN 0 MB 4 flag without clearing others*/
return RxID;
}

If I pass msg id 101 also it accepts

Could please tell what step i missing in CAN configuration

Re: can message mailbox filter

PetrS — Wed, 06 Apr 2022 10:36:18 GMT

Hi,

still you are using global masking scheme as finaly you have CAN0->MCR = 0x0000001F; thats clear IMRQ. So as you have RXMGMASK = 0, all IDs will be received.

Try to use below code

void FLEXCAN0_init(void)
{
#define MSG_BUF_SIZE 4 /* Msg Buffer Size. (CAN 2.0AB: 2 hdr + 2 data= 4 words) */
uint32_t i=0;

PCC->PCCn[PCC_FlexCAN0_INDEX] |= PCC_PCCn_CGC_MASK; /* CGC=1: enable clock to FlexCAN0 */

CAN0->MCR |= CAN_MCR_MDIS_MASK; /* MDIS=1: Disable module before selecting clock */
CAN0->CTRL1 &= ~CAN_CTRL1_CLKSRC_MASK; /* CLKsrc=0: Clock Source = SOSCDIV2 */
CAN0->MCR &= ~CAN_MCR_MDIS_MASK; /* MDIS=0; Enable module config. (Sets FRZ, HALT) */

while (!((CAN0->MCR & CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT)) {}
/*!
* Good practice:
* ===================================================
* wait for FRZACK=1 on freeze mode entry/exit
*/
CAN0->MCR |= CAN_MCR_IRMQ_MASK // enable individual mask registers
|CAN_MCR_SRXDIS_MASK // disable self reception
|CAN_MCR_MAXMB(31); // enable to use up to 32 MBs

uint32_t PRESDIV = 8000000 / (16*bps) -1;
/* Good practice: wait for FRZACK=1 on freeze mode entry/exit */
CAN0->CTRL1 = 0x00DB0006 | (PRESDIV<<24);

for(i=0; i<128; i++ )
{ /* CAN0: clear 32 msg bufs x 4 words/msg buf = 128 words */
CAN0->RAMn[i] = 0; /* Clear msg buf word */
}
for(i=0; i<32; i++ )
{ /* In FRZ mode, init CAN0 32 msg buf filters */
CAN0->RXIMR[i] = 0xFFFFFFFF; /* Check all ID bits for incoming messages */
}
CAN0->RXMGMASK = 0x1FFFFFFF; /* Global acceptance mask: check all ID bits */

CAN0->RAMn[4 * MSG_BUF_SIZE + 1] = 0x201<<18;//RxID; /* Msg Buf 4, word 1: Standard ID =*/
CAN0->RAMn[4 * MSG_BUF_SIZE + 0] = 0x4<<24;

CAN0->RXIMR[4] = 0x3F0<<18; // set mask register to allow Standard ID range = 0x200-0x20F

CAN0->MCR &= ~CAN_MCR_HALT_MASK; // negate HALT bit

while ((CAN0->MCR && CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT) {}
/* Good practice: wait for FRZACK to clear (not in freeze mode) */

while ((CAN0->MCR && CAN_MCR_NOTRDY_MASK) >> CAN_MCR_NOTRDY_SHIFT) {}
/* Good practice: wait for NOTRDY to clear (module ready) */
}

BR, Petr

Re: can message mailbox filter

AparnaSridharan — Thu, 07 Apr 2022 05:23:09 GMT

Hi @PetrS ,

I tried to configure Flex CAN with your code. But I cannot receive message. When I tried to transmit message from vehicle SPY it shows Tx message is aborted for all id. When i tried to pass message with id 201 also the buffer is not filled with mesage. but i can see id alone.

For your reference I have attached MCR register.

Could please tell what I have missed?

Re: can message mailbox filter

PetrS — Thu, 07 Apr 2022 09:07:47 GMT

Hi,

is FlexCAN running, or your code is running? From your picture FlexCAN is in freeze mode, so do not communicate. Try to clear FRZ bit too so module will run when debugger is stopped.
Do you have RXIMR really set?
Do you see any kind of error? check ECR/ESR1 registers.

BR, Petr