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    <title>S32KのトピックDifference between module clock and CHI clock in FlexCAN</title>
    <link>https://community.nxp.com/t5/S32K/Difference-between-module-clock-and-CHI-clock-in-FlexCAN/m-p/1435600#M14673</link>
    <description>&lt;P&gt;Hi NXP,&lt;/P&gt;&lt;P&gt;i am bit confuse between the &lt;STRONG&gt;module clock&lt;/STRONG&gt; and &lt;STRONG&gt;CHI clock&amp;nbsp;&lt;/STRONG&gt;of FlexCAN module (as shown in image)of S32K.&lt;/P&gt;&lt;P&gt;Plz explain the difference and their uses.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="KKumar_0-1648561780409.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/175181i1FDF822CC33E00BF/image-size/medium?v=v2&amp;amp;px=400" role="button" title="KKumar_0-1648561780409.png" alt="KKumar_0-1648561780409.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Tue, 29 Mar 2022 13:50:26 GMT</pubDate>
    <dc:creator>KKumar</dc:creator>
    <dc:date>2022-03-29T13:50:26Z</dc:date>
    <item>
      <title>Difference between module clock and CHI clock in FlexCAN</title>
      <link>https://community.nxp.com/t5/S32K/Difference-between-module-clock-and-CHI-clock-in-FlexCAN/m-p/1435600#M14673</link>
      <description>&lt;P&gt;Hi NXP,&lt;/P&gt;&lt;P&gt;i am bit confuse between the &lt;STRONG&gt;module clock&lt;/STRONG&gt; and &lt;STRONG&gt;CHI clock&amp;nbsp;&lt;/STRONG&gt;of FlexCAN module (as shown in image)of S32K.&lt;/P&gt;&lt;P&gt;Plz explain the difference and their uses.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="KKumar_0-1648561780409.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/175181i1FDF822CC33E00BF/image-size/medium?v=v2&amp;amp;px=400" role="button" title="KKumar_0-1648561780409.png" alt="KKumar_0-1648561780409.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 29 Mar 2022 13:50:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/Difference-between-module-clock-and-CHI-clock-in-FlexCAN/m-p/1435600#M14673</guid>
      <dc:creator>KKumar</dc:creator>
      <dc:date>2022-03-29T13:50:26Z</dc:date>
    </item>
    <item>
      <title>Re: Difference between module clock and CHI clock in FlexCAN</title>
      <link>https://community.nxp.com/t5/S32K/Difference-between-module-clock-and-CHI-clock-in-FlexCAN/m-p/1435814#M14677</link>
      <description>&lt;P&gt;&lt;A href="mailto:Hi@KKumar" target="_blank"&gt;Hi@KKumar&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;below infos comes from S32K-RM &lt;FONT color="#0000FF"&gt;Chapter 55.2.1 Overview&lt;/FONT&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Senlent_0-1648605507919.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/175220iFFB341C8AE96FC8E/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Senlent_0-1648605507919.png" alt="Senlent_0-1648605507919.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;The Protocol Engine (PE) submodule manages the serial communication on the CAN&lt;/P&gt;
&lt;P&gt;bus:&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;Requesting RAM access for receiving and transmitting message frames&lt;/LI&gt;
&lt;LI&gt;Validating received messages&lt;/LI&gt;
&lt;LI&gt;Performing error handling&lt;/LI&gt;
&lt;LI&gt;Detecting CAN FD messages&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;The Controller Host Interface (CHI) submodule manages message buffer selection for&lt;/P&gt;
&lt;P&gt;reception and transmission, taking care of arbitration and ID matching algorithms for&lt;/P&gt;
&lt;P&gt;both CAN FD and non-CAN FD message formats.&lt;/P&gt;
&lt;P&gt;The Bus Interface Unit (BIU) submodule controls access to and from the internal&lt;/P&gt;
&lt;P&gt;interface bus, in order to establish connection to the CPU and to other blocks. Clocks,&lt;/P&gt;
&lt;P&gt;address and data buses, interrupt outputs, DMA and test signals are accessed through the&lt;/P&gt;
&lt;P&gt;BIU.&lt;/P&gt;
&lt;P&gt;BR!&lt;/P&gt;
&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; Jim,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 30 Mar 2022 02:00:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/Difference-between-module-clock-and-CHI-clock-in-FlexCAN/m-p/1435814#M14677</guid>
      <dc:creator>Senlent</dc:creator>
      <dc:date>2022-03-30T02:00:55Z</dc:date>
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