topic S32K344 IO_MUX Clarifications in S32K https://community.nxp.com/t5/S32K/S32K344-IO-MUX-Clarifications/m-p/1419727#M14169 <P>With respect IO_Mux.xlx, I have&nbsp; below questions:</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Vijay_Arwapally_0-1645783794628.png" style="width: 400px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/171789i4A8497B96D8A5FFB/image-size/medium?v=v2&amp;px=400" role="button" title="Vijay_Arwapally_0-1645783794628.png" alt="Vijay_Arwapally_0-1645783794628.png" /></span></P><P>&nbsp;</P><P>Why is the direction for LPSPI1_SIN set to O-output??</P><P>There is no mention of IMCR in port configuration? Is it required to refer and use IMCR rows for port pins whenever the pin is required to be configured as input and ignore Mscr row?</P><P>Can you please clarify the doubts?</P> Fri, 25 Feb 2022 10:10:41 GMT Vijay_Arwapally 2022-02-25T10:10:41Z S32K344 IO_MUX Clarifications https://community.nxp.com/t5/S32K/S32K344-IO-MUX-Clarifications/m-p/1419727#M14169 <P>With respect IO_Mux.xlx, I have&nbsp; below questions:</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Vijay_Arwapally_0-1645783794628.png" style="width: 400px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/171789i4A8497B96D8A5FFB/image-size/medium?v=v2&amp;px=400" role="button" title="Vijay_Arwapally_0-1645783794628.png" alt="Vijay_Arwapally_0-1645783794628.png" /></span></P><P>&nbsp;</P><P>Why is the direction for LPSPI1_SIN set to O-output??</P><P>There is no mention of IMCR in port configuration? Is it required to refer and use IMCR rows for port pins whenever the pin is required to be configured as input and ignore Mscr row?</P><P>Can you please clarify the doubts?</P> Fri, 25 Feb 2022 10:10:41 GMT https://community.nxp.com/t5/S32K/S32K344-IO-MUX-Clarifications/m-p/1419727#M14169 Vijay_Arwapally 2022-02-25T10:10:41Z Re: S32K344 IO_MUX Clarifications https://community.nxp.com/t5/S32K/S32K344-IO-MUX-Clarifications/m-p/1419849#M14175 <P>Hi,</P> <P>this is because&nbsp;the SIN and SOUT pins can be configured to swap directions, so SIN can be output as well. Refer to LPSPI CFGR1[PINCFG] description.</P> <P>If SIN pin is input then you need to set MSCR[IBE] and respective IMCR[SSS].</P> <P><SPAN>BR, Petr</SPAN></P> Fri, 25 Feb 2022 14:33:46 GMT https://community.nxp.com/t5/S32K/S32K344-IO-MUX-Clarifications/m-p/1419849#M14175 PetrS 2022-02-25T14:33:46Z