<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: S32K344 RMII + QSPI in S32K</title>
    <link>https://community.nxp.com/t5/S32K/S32K344-RMII-QSPI/m-p/1417641#M14092</link>
    <description>&lt;P&gt;Hi Marco,&lt;/P&gt;
&lt;P&gt;let me check this. I will let you know the result later.&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Lukas&lt;/P&gt;</description>
    <pubDate>Tue, 22 Feb 2022 17:18:08 GMT</pubDate>
    <dc:creator>lukaszadrapa</dc:creator>
    <dc:date>2022-02-22T17:18:08Z</dc:date>
    <item>
      <title>S32K344 RMII + QSPI</title>
      <link>https://community.nxp.com/t5/S32K/S32K344-RMII-QSPI/m-p/1416828#M14071</link>
      <description>&lt;P&gt;Is it really possible to use at the same time both QSPI and RMII interfaces on S32K344 MQFP172?&lt;/P&gt;&lt;P&gt;According to&amp;nbsp;S32K3X4EVB-Q172 schematics/notes the answer seems to be yes.&lt;/P&gt;&lt;P&gt;But, checking the IOMUX spreadsheet, this part seems to lack of &lt;EM&gt;medium&lt;/EM&gt; or &lt;EM&gt;fast&lt;/EM&gt; pads and/or having a bad multiplexing: after selecting the fixed alternatives needed for the 6 QSPI signals, the RMII outputs TXEN, TXD1:0 can be only mapped to 25 MHz max&amp;nbsp;&lt;EM&gt;standard-plus&lt;/EM&gt; pads.&lt;/P&gt;&lt;P&gt;Any suggestion on what is wrong?&lt;/P&gt;</description>
      <pubDate>Mon, 21 Feb 2022 14:13:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K344-RMII-QSPI/m-p/1416828#M14071</guid>
      <dc:creator>marcoelia</dc:creator>
      <dc:date>2022-02-21T14:13:27Z</dc:date>
    </item>
    <item>
      <title>Re: S32K344 RMII + QSPI</title>
      <link>https://community.nxp.com/t5/S32K/S32K344-RMII-QSPI/m-p/1417641#M14092</link>
      <description>&lt;P&gt;Hi Marco,&lt;/P&gt;
&lt;P&gt;let me check this. I will let you know the result later.&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Lukas&lt;/P&gt;</description>
      <pubDate>Tue, 22 Feb 2022 17:18:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K344-RMII-QSPI/m-p/1417641#M14092</guid>
      <dc:creator>lukaszadrapa</dc:creator>
      <dc:date>2022-02-22T17:18:08Z</dc:date>
    </item>
    <item>
      <title>Re: S32K344 RMII + QSPI</title>
      <link>https://community.nxp.com/t5/S32K/S32K344-RMII-QSPI/m-p/1419597#M14162</link>
      <description>&lt;P&gt;Hi Marco,&lt;/P&gt;
&lt;P&gt;here is the response:&lt;/P&gt;
&lt;P&gt;"The S32K344EVB-Q172 was developed to support most of the functionalities of the MCU, on this time the Ethernet has routed the recommendation on the RM to support QSPI + MII. As you mentioned due to the pad type support RMII + QPSI is not possible for S32K344 devices."&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Lukas&lt;/P&gt;</description>
      <pubDate>Fri, 25 Feb 2022 07:14:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K344-RMII-QSPI/m-p/1419597#M14162</guid>
      <dc:creator>lukaszadrapa</dc:creator>
      <dc:date>2022-02-25T07:14:50Z</dc:date>
    </item>
    <item>
      <title>Re: S32K344 RMII + QSPI</title>
      <link>https://community.nxp.com/t5/S32K/S32K344-RMII-QSPI/m-p/1856731#M34782</link>
      <description>&lt;P&gt;Is this still the case, has silicon been improved?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 29 Apr 2024 12:26:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K344-RMII-QSPI/m-p/1856731#M34782</guid>
      <dc:creator>Fast</dc:creator>
      <dc:date>2024-04-29T12:26:11Z</dc:date>
    </item>
  </channel>
</rss>

