S32Kのトピックspi continuous frames cannot be implemented

spi continuous frames cannot be implemented

Xjh193 — Tue, 22 Feb 2022 02:44:21 GMT

I want to use lpspi1 as master to transmit 3 * 16 bit as a frame to slave MC33664.

But tx clk is not correct. when i send 48 bit as a frame ,the clk and data cs all waveform is correct and MC33664 return data can be received by lpspi2 as slave. when slave set LPSPI_TCR_FRAMESZ as 16 bit ,the receive data order is not correct. but set LPSPI_TCR_FRAMESZ as 48 bit is correct. I think it might be used not correctly of LPSPI_TCR_CONT and LPSPI_TCR_CONTC register .But I tried different combinations of these，none of them succeeded.

Please tell me how to configure a continuous frame. my code refer to attachment. Thank you.

Re: spi continuous frames cannot be implemented

danielmartynek — Tue, 22 Feb 2022 11:20:17 GMT

Hi @Xjh193,

This is you code:

In the first command, you have both CONT can CONTC set.

But only CONT should be set, becasuse it starts a new continuous transfer (CONT = 1) but it does not change an ongoing continuous transfer (CONTC = 0).

Then, you can write all the three 16bit words (please check if there is a place in the FIFO left).

And terminate the continuous transfer with a new command where (CONT = 0, CONTC = 0).

There is actualy no need for CONTC = 1, becasue you don't change any parameters of the continous transfer specified in the first command, you just start it and terminate it.

Regards,

Daniel

Re: spi continuous frames cannot be implemented

Xjh193 — Wed, 23 Feb 2022 12:21:35 GMT

hi@Daniel, accoding to your guidance ,I sent 0x1122 0x3344 0x5566 data and get them. Thank you!

Now I want to use DMA channel to receive spi data,but failed. I check the related register , found that the TCD0_DADDR are not added. I enable DMAMUX_0, DMA_TCD0 clock. source 48(lspi2 rx request) ,DMA channel 0. See the attachment for the more configuration. I'm looking forward to you reply.

Re: spi continuous frames cannot be implemented

danielmartynek — Thu, 24 Feb 2022 08:34:34 GMT

Hi@Xjh193 ,

Please create a new thread regarding the DMA.

BR, Daniel