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    <title>topic Re: S32K344 SPI Master TX in S32K</title>
    <link>https://community.nxp.com/t5/S32K/S32K344-SPI-Master-TX/m-p/1415664#M14049</link>
    <description>&lt;P&gt;hi&amp;nbsp;@&lt;SPAN&gt;Daniel&lt;/SPAN&gt;, the bug cause we found slow clock is not configured by MCU_CGM register.&lt;/P&gt;&lt;P&gt;Thank you！&lt;/P&gt;</description>
    <pubDate>Fri, 18 Feb 2022 02:12:35 GMT</pubDate>
    <dc:creator>Xjh193</dc:creator>
    <dc:date>2022-02-18T02:12:35Z</dc:date>
    <item>
      <title>S32K344 SPI Master TX</title>
      <link>https://community.nxp.com/t5/S32K/S32K344-SPI-Master-TX/m-p/1414296#M14018</link>
      <description>&lt;P&gt;Hello，when i used s32k344 , I want to send a frame of 32 bit by LPSPI1. But&amp;nbsp; I get two frame of 32 bit on an oscilloscope. How is SPI module&amp;nbsp; configurated reference attachement. The same is true for other SPI modules. Please help me !&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Xjh193_0-1645001402054.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/170722iDBD8FDEFA81B8162/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Xjh193_0-1645001402054.png" alt="Xjh193_0-1645001402054.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 16 Feb 2022 08:58:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K344-SPI-Master-TX/m-p/1414296#M14018</guid>
      <dc:creator>Xjh193</dc:creator>
      <dc:date>2022-02-16T08:58:04Z</dc:date>
    </item>
    <item>
      <title>Re: S32K344 SPI Master TX</title>
      <link>https://community.nxp.com/t5/S32K/S32K344-SPI-Master-TX/m-p/1414476#M14021</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/181697"&gt;@Xjh193&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;If TXMSK = 0, a new transfer is initiated only when the Transmit Data Register is written, so, if there is only one 32bit write to the FIFO, the module should send just one 32bit frame (FRAMESZ = 31).&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Do you need to reset the FIFOs in the function?&lt;/P&gt;
&lt;P&gt;There is an erratum regarding the FIFO reset:&lt;/P&gt;
&lt;P&gt;ERR050456: LPSPI: Reset to fifo does not work as expected&lt;/P&gt;
&lt;P&gt;&lt;A href="https://www.nxp.com/webapp/Download?colCode=S32K3X4-0P55A-1P55A-ERRATA" target="_blank"&gt;https://www.nxp.com/webapp/Download?colCode=S32K3X4-0P55A-1P55A-ERRATA&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Can you please try without the two writes to the Control Register?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Daniel&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 16 Feb 2022 13:25:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K344-SPI-Master-TX/m-p/1414476#M14021</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2022-02-16T13:25:22Z</dc:date>
    </item>
    <item>
      <title>Re: S32K344 SPI Master TX</title>
      <link>https://community.nxp.com/t5/S32K/S32K344-SPI-Master-TX/m-p/1415664#M14049</link>
      <description>&lt;P&gt;hi&amp;nbsp;@&lt;SPAN&gt;Daniel&lt;/SPAN&gt;, the bug cause we found slow clock is not configured by MCU_CGM register.&lt;/P&gt;&lt;P&gt;Thank you！&lt;/P&gt;</description>
      <pubDate>Fri, 18 Feb 2022 02:12:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K344-SPI-Master-TX/m-p/1415664#M14049</guid>
      <dc:creator>Xjh193</dc:creator>
      <dc:date>2022-02-18T02:12:35Z</dc:date>
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