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    <title>topic Re: Interrupt Priorty Issue in S32K</title>
    <link>https://community.nxp.com/t5/S32K/Interrupt-Priorty-Issue/m-p/705752#M1391</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Daniel,&lt;/P&gt;&lt;P&gt;Thank you!&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 24 Aug 2017 04:40:56 GMT</pubDate>
    <dc:creator>shaileshagrahar</dc:creator>
    <dc:date>2017-08-24T04:40:56Z</dc:date>
    <item>
      <title>Interrupt Priorty Issue</title>
      <link>https://community.nxp.com/t5/S32K/Interrupt-Priorty-Issue/m-p/705750#M1389</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I am using S32K144 micro controller . In this controller there are 16 interrupt level from 0 to 15.&lt;/P&gt;&lt;P&gt;In my application i am using two interrupt source and assigned priority 0 and 5 to both the interrupt source.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Now at some state in my code i am disabling the both interrupts ( i am using&amp;nbsp; &lt;STRONG&gt;BASEPRI&lt;/STRONG&gt; register to disable ).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;So keeping in mind the above situation i have loaded &lt;STRONG&gt;BASEPRI&lt;/STRONG&gt;= 0x000000&lt;STRONG&gt;00 &lt;/STRONG&gt;to disable all interrupt having priorty level 0 and lower than 0 (means 5). But i am still getting interrupts,even i have disabled the interrupts.&lt;/P&gt;&lt;P&gt;Is this issue due to that i am putting "&lt;STRONG&gt;BASEPRI&lt;/STRONG&gt;= 0x000000&lt;STRONG&gt;00&lt;/STRONG&gt;"?&lt;/P&gt;&lt;P&gt;because Priority mask bits:&lt;CODE class=""&gt;0x00&lt;/CODE&gt; = no effect,as given in this manual&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0321a/index.html" title="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0321a/index.html"&gt;ARM Information Center&lt;/A&gt; .&lt;/P&gt;&lt;P&gt;Could you please help me on this.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 23 Aug 2017 16:12:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/Interrupt-Priorty-Issue/m-p/705750#M1389</guid>
      <dc:creator>shaileshagrahar</dc:creator>
      <dc:date>2017-08-23T16:12:55Z</dc:date>
    </item>
    <item>
      <title>Re: Interrupt Priorty Issue</title>
      <link>https://community.nxp.com/t5/S32K/Interrupt-Priorty-Issue/m-p/705751#M1390</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;The BASEPRI register must be set to nonzero value in order to mask interrupts that have the same or lower interrupt priority. If you need to mask all interrupts including those with interrupt priority 0, then set PRIMASK bit.&lt;/P&gt;&lt;PRE class="language-none line-numbers"&gt;&lt;CODE&gt;__asm("cpsid i") // Disable interrupts
__asm("cpsie i") // Enable interrupts&lt;SPAN class="line-numbers-rows"&gt;&lt;SPAN&gt;‍&lt;/SPAN&gt;&lt;SPAN&gt;‍&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/CODE&gt;&lt;/PRE&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Daniel&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 23 Aug 2017 20:49:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/Interrupt-Priorty-Issue/m-p/705751#M1390</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2017-08-23T20:49:58Z</dc:date>
    </item>
    <item>
      <title>Re: Interrupt Priorty Issue</title>
      <link>https://community.nxp.com/t5/S32K/Interrupt-Priorty-Issue/m-p/705752#M1391</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Daniel,&lt;/P&gt;&lt;P&gt;Thank you!&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 24 Aug 2017 04:40:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/Interrupt-Priorty-Issue/m-p/705752#M1391</guid>
      <dc:creator>shaileshagrahar</dc:creator>
      <dc:date>2017-08-24T04:40:56Z</dc:date>
    </item>
    <item>
      <title>Re: Interrupt Priorty Issue</title>
      <link>https://community.nxp.com/t5/S32K/Interrupt-Priorty-Issue/m-p/1152943#M8143</link>
      <description>&lt;P&gt;How do you set BASEPRI?&lt;/P&gt;&lt;P&gt;s32_core_cm4.h has macros for cpsie and cpsid, but nothing for BASEPRI register.&lt;/P&gt;&lt;P&gt;I am looking for something like this:&amp;nbsp;&lt;/P&gt;&lt;PRE&gt;// code before critical section&lt;BR /&gt;__set_BASEPRI(6 &amp;lt;&amp;lt; (8 - __NVIC_PRIO_BITS));&lt;BR /&gt;// critical section&lt;BR /&gt;__set_BASEPRI(0U); // remove the BASEPRI masking&lt;BR /&gt;// code after critical section&lt;/PRE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;described here:&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.arm.com/developer/ip-products/system/b/embedded-blog/posts/cutting-through-the-confusion-with-arm-cortex-m-interrupt-priorities" target="_blank" rel="noopener"&gt;https://community.arm.com/developer/ip-products/system/b/embedded-blog/posts/cutting-through-the-confusion-with-arm-cortex-m-interrupt-priorities&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 14 Sep 2020 14:31:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/Interrupt-Priorty-Issue/m-p/1152943#M8143</guid>
      <dc:creator>m_mishrikey</dc:creator>
      <dc:date>2020-09-14T14:31:52Z</dc:date>
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