topic EWM and WDOG's refresh sequence in S32K

EWM and WDOG's refresh sequence

GoldenStateWarriorCurry — Thu, 09 Dec 2021 02:03:05 GMT

Hello,

Christmas is coming soon, congratulations to everyone in advance .

I am using EWM and WDOG module in S32K146，and have some questions about EWM and WDOG's application habits：

WDOG supports one 32-bit (0xB480_A602) if WDOG_CS[CMD32EN] is 1, however, EWM must two 8bit writes(one sequence). Why I can‘t write one value like WDOG without one sequence .

What accidents can be prevented by this sequence ？If you guys have any advices for sequence , please help.

Thanks!

Re: EWM and WDOG's refresh sequence

Senlent — Thu, 09 Dec 2021 05:43:05 GMT

Hi@GoldenStateWarriorCurry

Please refer to S32K-RM for details.

20.4 Memory Map/Register Definition
This section contains the module memory map and registers.

NOTE:

EWM only supports 8-bit register access. 16-bit and 32-bit access are not possible.

BR!

Jim,

Re: EWM and WDOG's refresh sequence

GoldenStateWarriorCurry — Thu, 09 Dec 2021 09:48:52 GMT

Hi@Senlent

Thank you for your reply!

I have read 20.4 Memory Map/Register Definition from S32K-RM.

I just don't understand why I can't write values of 0xB4 to refresh EWM counter instead of writing values of 0xB4 and 0x2C to refresh EWM counter.

As a user, I feel that it is troublesome to write the refresh register twice. What accidents can be prevented by writing the refresh register twice.

If you are worried about safety issues, can we write 32-bit values once instead of writing values of 0xB4 and 0x2C to refresh EWM counter,which likes WDOG refresh mechanism.

I hope NXP company can adopt my suggestion to optimize user usage .=^-^=

BR!

Anthony,