topic Re: s32k14x PLL Frequency Tolerance in S32K

s32k14x PLL Frequency Tolerance

Mimo88 — Thu, 15 Oct 2020 15:10:19 GMT

I'm trying to figure out the S32k14x PLL frequency tolerance, I found in the data sheet the following table that specify the lock exit frequency tolerance Dunl value. I'm a little bit confused if this value represent the PLL frequency tolerance. if no where i can find this info?

Re: s32k14x PLL Frequency Tolerance

danielmartynek — Fri, 16 Oct 2020 08:48:37 GMT

Hello,

The table specifies typ. PLL Jitter over one PLL period and accumulated jitter over 1us.

BR, Daniel

Re: s32k14x PLL Frequency Tolerance

gobrien8 — Wed, 06 Jan 2021 19:06:47 GMT

Daniel,

I have the same question about the PLL Lock Exit Frequency Tolerance. If we are trying to quantify the overall PLL timing error say over a 1uS period, is the long term jitter all that we consider? Does the PLL Lock Exit Frequency Tolerance have any bearing on the timing error in this case?

Re: s32k14x PLL Frequency Tolerance

aceangle — Fri, 05 Nov 2021 03:35:18 GMT

it seems the accuracy is kind of high. say Fvco_clk =320M, the period is 3.125ns, so the tolerance is 75ps/3.125ns=2.4%.

but I do not know whether the calculation method is right or not. maybe there exists other calculation method I do not know.

do you have any ideas?

Re: s32k14x PLL Frequency Tolerance

aceangle — Fri, 05 Nov 2021 03:47:41 GMT

Hi, Daniel

Could you please show how to calculate the accuracy of PLL? let's say Fvco_clk=320MHz. could you show the detailed calculation?

is the calculation right or not: 75ps/(1000/320ns)=2.4% ?

I also have to calculate UART baudrate(20kbps) accuracy, which is derived from SPLL_CLK.