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    <title>topic Read FCSESTAT register value in S32K</title>
    <link>https://community.nxp.com/t5/S32K/Read-FCSESTAT-register-value/m-p/1364136#M12623</link>
    <description>&lt;P&gt;If I am on a new chip without flash partition and CSEC enable, can I read the value of FCSESTAT register? If yes, is the value of FCSESTAT [sb] = 0?&lt;/P&gt;</description>
    <pubDate>Sat, 30 Oct 2021 11:02:15 GMT</pubDate>
    <dc:creator>wang_q4</dc:creator>
    <dc:date>2021-10-30T11:02:15Z</dc:date>
    <item>
      <title>Read FCSESTAT register value</title>
      <link>https://community.nxp.com/t5/S32K/Read-FCSESTAT-register-value/m-p/1364136#M12623</link>
      <description>&lt;P&gt;If I am on a new chip without flash partition and CSEC enable, can I read the value of FCSESTAT register? If yes, is the value of FCSESTAT [sb] = 0?&lt;/P&gt;</description>
      <pubDate>Sat, 30 Oct 2021 11:02:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/Read-FCSESTAT-register-value/m-p/1364136#M12623</guid>
      <dc:creator>wang_q4</dc:creator>
      <dc:date>2021-10-30T11:02:15Z</dc:date>
    </item>
    <item>
      <title>Re: Read FCSESTAT register value</title>
      <link>https://community.nxp.com/t5/S32K/Read-FCSESTAT-register-value/m-p/1364219#M12625</link>
      <description>&lt;P&gt;&lt;A href="mailto:Hi@wang_q4" target="_blank"&gt;Hi@wang_q4&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; Please refers to :chapter :36.4.4.1.10 Flash CSEc Status Register (FCSESTAT)&lt;/P&gt;
&lt;P&gt;&lt;FONT color="#0000FF"&gt;&lt;STRONG&gt;Table 36-27. Boot/MAC map to CSEc Status Flags (S32K RM)&lt;/STRONG&gt;&lt;/FONT&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Senlent_0-1635731339348.png" style="width: 639px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/160784i65CFBB5B3D417E69/image-dimensions/639x261?v=v2" width="639" height="261" role="button" title="Senlent_0-1635731339348.png" alt="Senlent_0-1635731339348.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;Know more detail:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://www.nxp.com/search?keyword=AN5401&amp;amp;start=0" target="_self"&gt;https://www.nxp.com/search?keyword=AN5401&amp;amp;start=0&lt;/A&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; Obviously, when using a new chip , FCSESTAT[SB] should be set to 0 upon reset.&lt;/P&gt;
&lt;P&gt;BR!&lt;/P&gt;
&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;Jim,&lt;/P&gt;</description>
      <pubDate>Mon, 01 Nov 2021 01:58:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/Read-FCSESTAT-register-value/m-p/1364219#M12625</guid>
      <dc:creator>Senlent</dc:creator>
      <dc:date>2021-11-01T01:58:53Z</dc:date>
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