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    <title>S32KのトピックS32K148 QSPI clock settings issue</title>
    <link>https://community.nxp.com/t5/S32K/S32K148-QSPI-clock-settings-issue/m-p/1330421#M11849</link>
    <description>&lt;P&gt;Hi.&lt;BR /&gt;I work with EVB and using QSPI example from S32 Design Studio. Goal: SCLK = 80MHz&lt;BR /&gt;Using PLL_DIV1 and various settings max 20Mhz works.&lt;BR /&gt;Default project settings use FIRC and divider set to 4.&amp;nbsp;&lt;BR /&gt;Has anyone tried to change QSPI frequency in this example?&amp;nbsp;&lt;/P&gt;&lt;P&gt;Any ideas?&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Thu, 26 Aug 2021 14:05:14 GMT</pubDate>
    <dc:creator>Konrad_M</dc:creator>
    <dc:date>2021-08-26T14:05:14Z</dc:date>
    <item>
      <title>S32K148 QSPI clock settings issue</title>
      <link>https://community.nxp.com/t5/S32K/S32K148-QSPI-clock-settings-issue/m-p/1330421#M11849</link>
      <description>&lt;P&gt;Hi.&lt;BR /&gt;I work with EVB and using QSPI example from S32 Design Studio. Goal: SCLK = 80MHz&lt;BR /&gt;Using PLL_DIV1 and various settings max 20Mhz works.&lt;BR /&gt;Default project settings use FIRC and divider set to 4.&amp;nbsp;&lt;BR /&gt;Has anyone tried to change QSPI frequency in this example?&amp;nbsp;&lt;/P&gt;&lt;P&gt;Any ideas?&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 26 Aug 2021 14:05:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K148-QSPI-clock-settings-issue/m-p/1330421#M11849</guid>
      <dc:creator>Konrad_M</dc:creator>
      <dc:date>2021-08-26T14:05:14Z</dc:date>
    </item>
    <item>
      <title>Re: S32K148 QSPI clock settings issue</title>
      <link>https://community.nxp.com/t5/S32K/S32K148-QSPI-clock-settings-issue/m-p/1330701#M11854</link>
      <description>&lt;P&gt;Hi&amp;nbsp;Konrad_M,&lt;/P&gt;
&lt;P&gt;Maybe you can refer the method shown below:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="change clock.png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/154273i46BE7386E2F0B026/image-size/large?v=v2&amp;amp;px=999" role="button" title="change clock.png" alt="change clock.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;Best Regards,&lt;BR /&gt;Robin&lt;BR /&gt;-------------------------------------------------------------------------------&lt;BR /&gt;Note:&lt;BR /&gt;- If this post answers your question, please click the "Mark Correct" button. Thank you!&lt;/P&gt;
&lt;P&gt;- We are following threads for 7 weeks after the last post, later replies are ignored&lt;BR /&gt;Please open a new thread and refer to the closed one, if you have a related question at a later point in time.&lt;BR /&gt;-------------------------------------------------------------------------------&lt;/P&gt;</description>
      <pubDate>Fri, 27 Aug 2021 03:04:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K148-QSPI-clock-settings-issue/m-p/1330701#M11854</guid>
      <dc:creator>Robin_Shen</dc:creator>
      <dc:date>2021-08-27T03:04:57Z</dc:date>
    </item>
    <item>
      <title>Re: S32K148 QSPI clock settings issue</title>
      <link>https://community.nxp.com/t5/S32K/S32K148-QSPI-clock-settings-issue/m-p/1330748#M11856</link>
      <description>&lt;P&gt;Using PLL, as shown, even 30MHz is too much....program stops and wait forever on last RX interrupt&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Konrad_M_0-1630038717407.png" style="width: 820px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/154279i5DA7D70DB7AC4989/image-dimensions/820x689?v=v2" width="820" height="689" role="button" title="Konrad_M_0-1630038717407.png" alt="Konrad_M_0-1630038717407.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Konrad_M_1-1630038850393.png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/154280i8807B7CB758D9F40/image-size/large?v=v2&amp;amp;px=999" role="button" title="Konrad_M_1-1630038850393.png" alt="Konrad_M_1-1630038850393.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 27 Aug 2021 04:35:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K148-QSPI-clock-settings-issue/m-p/1330748#M11856</guid>
      <dc:creator>Konrad_M</dc:creator>
      <dc:date>2021-08-27T04:35:15Z</dc:date>
    </item>
    <item>
      <title>Re: S32K148 QSPI clock settings issue</title>
      <link>https://community.nxp.com/t5/S32K/S32K148-QSPI-clock-settings-issue/m-p/1330788#M11857</link>
      <description>&lt;P&gt;Can SPLLDIV2_CLK be set with 80Mhz?&lt;/P&gt;&lt;P&gt;I checked the datasheet it should be less than the one in the below?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="yihe_zuo_0-1630042915312.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/154289iAE16684373C25E69/image-size/medium?v=v2&amp;amp;px=400" role="button" title="yihe_zuo_0-1630042915312.png" alt="yihe_zuo_0-1630042915312.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;Could you double check?&lt;/P&gt;</description>
      <pubDate>Fri, 27 Aug 2021 05:42:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K148-QSPI-clock-settings-issue/m-p/1330788#M11857</guid>
      <dc:creator>yihe_zuo</dc:creator>
      <dc:date>2021-08-27T05:42:56Z</dc:date>
    </item>
    <item>
      <title>Re: S32K148 QSPI clock settings issue</title>
      <link>https://community.nxp.com/t5/S32K/S32K148-QSPI-clock-settings-issue/m-p/1330805#M11859</link>
      <description>&lt;P&gt;Good point but didn't help.&lt;BR /&gt;&lt;SPAN&gt;SPLLDIV2_CLK should be 40Mhz or less but QSPI uses&amp;nbsp;SPLLDIV1_CLK.&lt;BR /&gt;Thank you.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 27 Aug 2021 06:08:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K148-QSPI-clock-settings-issue/m-p/1330805#M11859</guid>
      <dc:creator>Konrad_M</dc:creator>
      <dc:date>2021-08-27T06:08:56Z</dc:date>
    </item>
    <item>
      <title>Re: S32K148 QSPI clock settings issue</title>
      <link>https://community.nxp.com/t5/S32K/S32K148-QSPI-clock-settings-issue/m-p/1335666#M11993</link>
      <description>&lt;P&gt;&lt;SPAN&gt;Hi&amp;nbsp;Konrad_M,&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;Sorry for my last reply.&lt;BR /&gt;I confused the QSPI and LSPI routines. &lt;BR /&gt;After modify the S32K148EVB circuit and change the clock configuration, I encountered the same phenomenon you described.&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Hardware Wiring.png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/155236i3691919D69D82C68/image-size/large?v=v2&amp;amp;px=999" role="button" title="Hardware Wiring.png" alt="Hardware Wiring.png" /&gt;&lt;/span&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Wait for program to finish 76MHz div2.png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/155237iAA16F0561ED17DA5/image-size/large?v=v2&amp;amp;px=999" role="button" title="Wait for program to finish 76MHz div2.png" alt="Wait for program to finish 76MHz div2.png" /&gt;&lt;/span&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;According to the description of the Data Sheet "Table 39. QuadSPI electrical specifications", the&amp;nbsp;max SCK Clock Frequency of FLASH A PORT should be 38MHz when&amp;nbsp;Internal Sampling is selected.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Robin_Shen_0-1630975395135.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/155238i124E5AE70FDE20F8/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Robin_Shen_0-1630975395135.png" alt="Robin_Shen_0-1630975395135.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;I got their feedback after consulting the AE team:&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;I re-appeared the issue you describled. After anslysis, this issue is not caused by the clock frequency. when you read data and the size is larger than 256 bytes, it will happen the overflow error. so it will pending in that line. if I reallocated the read API into the write process, which read 256 bytes every time, it work well. That means the maximum clock frequency can reach 38MHz. about the overflow error, I will test it in the newest version. if still exist, I will create a ticket in our system.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Robin_Shen_1-1630975495560.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/155239i1086A53A5D0F95C0/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Robin_Shen_1-1630975495560.png" alt="Robin_Shen_1-1630975495560.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;Best Regards,&lt;BR /&gt;Robin&lt;BR /&gt;-------------------------------------------------------------------------------&lt;BR /&gt;Note:&lt;BR /&gt;- If this post answers your question, please click the "Mark Correct" button. Thank you!&lt;/P&gt;
&lt;P&gt;- We are following threads for 7 weeks after the last post, later replies are ignored&lt;BR /&gt;Please open a new thread and refer to the closed one, if you have a related question at a later point in time.&lt;BR /&gt;-------------------------------------------------------------------------------&lt;/P&gt;</description>
      <pubDate>Tue, 07 Sep 2021 00:47:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K148-QSPI-clock-settings-issue/m-p/1335666#M11993</guid>
      <dc:creator>Robin_Shen</dc:creator>
      <dc:date>2021-09-07T00:47:01Z</dc:date>
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