https://community.nxp.com/t5/S32K/S32K146-CSE-module-data-alignment-consultation/m-p/1275259#M10847 <P>From the description of the screenshot S32k reference manual, S32K uses big-endian alignment, but why the actual test is little-endian alignment</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="584914019_0-1620782896818.png" style="width: 400px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/144490i13012AFEA8941F89/image-size/medium?v=v2&amp;px=400" role="button" title="584914019_0-1620782896818.png" alt="584914019_0-1620782896818.png" /></span></P><P>&nbsp;</P> Wed, 12 May 2021 01:28:27 GMT 584914019 2021-05-12T01:28:27Z https://community.nxp.com/t5/S32K/S32K146-CSE-module-data-alignment-consultation/m-p/1275259#M10847 <P>From the description of the screenshot S32k reference manual, S32K uses big-endian alignment, but why the actual test is little-endian alignment</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="584914019_0-1620782896818.png" style="width: 400px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/144490i13012AFEA8941F89/image-size/medium?v=v2&amp;px=400" role="button" title="584914019_0-1620782896818.png" alt="584914019_0-1620782896818.png" /></span></P><P>&nbsp;</P> Wed, 12 May 2021 01:28:27 GMT https://community.nxp.com/t5/S32K/S32K146-CSE-module-data-alignment-consultation/m-p/1275259#M10847 584914019 2021-05-12T01:28:27Z https://community.nxp.com/t5/S32K/S32K146-CSE-module-data-alignment-consultation/m-p/1275397#M10854 <P>Hi&nbsp;<SPAN>xin tu</SPAN><SPAN>,</SPAN></P> <P>This documentation issue should have been fixed in latest <A href="https://www.nxp.com/webapp/Download?colCode=S32K1XXRM" target="_self">S32K1xx MCU Family - Reference Manual (REV 13)</A>.<BR />Here you can see the new description of "36.5.13.4 Generic PRAM interface description":</P> <P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="36.5.13.4 Generic PRAM interface description.jpg" style="width: 999px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/144511i27337D45482A47F9/image-size/large?v=v2&amp;px=999" role="button" title="36.5.13.4 Generic PRAM interface description.jpg" alt="36.5.13.4 Generic PRAM interface description.jpg" /></span></P> <P>Best Regards,<BR />Robin<BR />-------------------------------------------------------------------------------<BR />Note:<BR />- If this post answers your question, please click the "Mark Correct" button. Thank you!</P> <P>- We are following threads for 7 weeks after the last post, later replies are ignored<BR />Please open a new thread and refer to the closed one, if you have a related question at a later point in time.<BR />-------------------------------------------------------------------------------</P> <P>&nbsp;</P> Wed, 12 May 2021 06:52:33 GMT https://community.nxp.com/t5/S32K/S32K146-CSE-module-data-alignment-consultation/m-p/1275397#M10854 Robin_Shen 2021-05-12T06:52:33Z https://community.nxp.com/t5/S32K/S32K146-CSE-module-data-alignment-consultation/m-p/1275408#M10857 <P>thanks you very match</P> Wed, 12 May 2021 07:02:27 GMT https://community.nxp.com/t5/S32K/S32K146-CSE-module-data-alignment-consultation/m-p/1275408#M10857 584914019 2021-05-12T07:02:27Z