<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>S32Kのトピックpre-emption priority and subpriority</title>
    <link>https://community.nxp.com/t5/S32K/pre-emption-priority-and-subpriority/m-p/686798#M1083</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;it supports pre-emption priority and&lt;SPAN style="color: #000000;"&gt; subpriority &lt;/SPAN&gt;in S32K144?&lt;/P&gt;&lt;P&gt;and how to configure&amp;nbsp;it?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 07 Jul 2017 07:13:39 GMT</pubDate>
    <dc:creator>panda_fei</dc:creator>
    <dc:date>2017-07-07T07:13:39Z</dc:date>
    <item>
      <title>pre-emption priority and subpriority</title>
      <link>https://community.nxp.com/t5/S32K/pre-emption-priority-and-subpriority/m-p/686798#M1083</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;it supports pre-emption priority and&lt;SPAN style="color: #000000;"&gt; subpriority &lt;/SPAN&gt;in S32K144?&lt;/P&gt;&lt;P&gt;and how to configure&amp;nbsp;it?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 07 Jul 2017 07:13:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/pre-emption-priority-and-subpriority/m-p/686798#M1083</guid>
      <dc:creator>panda_fei</dc:creator>
      <dc:date>2017-07-07T07:13:39Z</dc:date>
    </item>
    <item>
      <title>Re: pre-emption priority and subpriority</title>
      <link>https://community.nxp.com/t5/S32K/pre-emption-priority-and-subpriority/m-p/686799#M1084</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The S32K144 MCU supports both.&lt;/P&gt;&lt;P&gt;There are 16 priority levels configurable in the 4 most significant bits in IRQn fields in NVIC IPRn registers. See Chapter 7.2.1. RM.&amp;nbsp; The lower the priority number is set, the higher priority. So priority 0 is the highest priority level. And all interrupts are set to this level out of reset.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Note: The S32_NVIC_IP_PRIn(x) function from the S32K144.h header file (S32DS) doesn’t shift the number to the 4 most significant bits of IRQn. Therefore, to set priority number 4, for instance, it is necessary to put it like this:&lt;/P&gt;&lt;P&gt;S32_NVIC-&amp;gt;IP[x] |= S32_NVIC_IP_PRIn(0x40); // priority number 4&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Preemption:&lt;/P&gt;&lt;P&gt;An interrupt with a higher priority level preempts an interrupt with lower priority level. For example, an interrupt with priority number 2 preempts interrupt with priority number 3 and higher.&lt;/P&gt;&lt;P&gt;If multiple pending interrupts have the same priority, the pending interrupt with the lowest exception number is executed first. &amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Subpriority:&lt;/P&gt;&lt;P&gt;Priority grouping is configurable in the AIRCR[PRIGROUP] register.&lt;/P&gt;&lt;P&gt;And it is well explained in &lt;A href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/DUI0553A_cortex_m4_dgug.pdf"&gt;ARM Cortex M4 Generic User Guide&lt;/A&gt;, Chapter 4.3.5.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;A number written to the PRIGROUP basically divides the IPRn[IRQn] to bits that configure the preemption and subpriorities. Since the S32K144 implements only 16 priority levels, configurable in the 4 most significant bits of IRQn, the PRIGROUP must be set to number that is greater or equal to 4.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Then, if PRIGROUP = 4, the IRQn[7-5] bits configure all preemptive interrupt levels and the IRQn[4] bit configures subpriority levels.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Note: By default, the AIRCR register is a read-only register. In order to set the PRIGROUP field, it is necessary to write to VECTKEYSTAT the number 0x5FA along with the PRIGROUP number, otherwise the processor ignores the write.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;S32_SCB-&amp;gt;AIRCR = 0x5FA0400;&amp;nbsp;&lt;/P&gt;&lt;P&gt;[31-16] VECTKEYSTAT = 0x5FA&lt;/P&gt;&lt;P&gt;[10-8] PRIGROUP = 0x4&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Daniel&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 09 Jul 2017 13:54:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/pre-emption-priority-and-subpriority/m-p/686799#M1084</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2017-07-09T13:54:28Z</dc:date>
    </item>
  </channel>
</rss>

