S32KのトピックRe: S32K118 I/O Characterization

S32K118 I/O Characterization

RomanPBudek — Wed, 05 May 2021 20:06:35 GMT

Customer would like to get information on the acceptable quality of the signal from key performance indicators on the microcontroller perspective on the receive side of the communication signal.

The datasheet does not provide acceptance criteria if the input signal Rise and Fall time as a percentage of the overall clock frequency/ Clock Low/High duration perspective

What would be the timing requirements accordingly:

Diagram	Measurements	Acceptance criteria
RomanPBudek_0-1620245151341.jpeg	This diagram shows horizontal cursors at 20% and 80% of the signal amplitude. The fall time measurement is captured as 11.6ns	Please provide an acceptable Fall time range
RomanPBudek_1-1620245151356.jpeg	This diagram shows the same signal measuring Clock High duration, which is 83.2ns
RomanPBudek_2-1620245151370.jpeg	This diagram shows horizontal cursors at 20% and 80% of the signal amplitude. The fall time measurement is captured as 10ns	Please provide an acceptable Rise time range

Re: S32K118 I/O Characterization

davidtosenovjan — Thu, 06 May 2021 12:36:39 GMT

Hi, could you clarify which specific peripheral is this question related to?

Re: S32K118 I/O Characterization

RomanPBudek — Wed, 12 May 2021 21:16:38 GMT

The customer will be using a variety of peripherals which include I2C, SPI, UART, Ethernet, FlexIO an others. Can NXP provide a white paper or calculator for determining this data for each peripheral.

@davidtosenovjan

Re: S32K118 I/O Characterization

davidtosenovjan — Thu, 13 May 2021 12:17:53 GMT

It is not being so explicitly defined unless it is required by certain peripheral, otherwise it is stated in device datasheet. With this device I see such specification in LPSPI module.

In other aspect in is just CMOS with hysteresis, length of edges is not important unless it affect setup/hold time or other AC characteristic of specific peripheral.