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    <title>topic UART DMA (time gap between bytes) in S32K</title>
    <link>https://community.nxp.com/t5/S32K/UART-DMA-time-gap-between-bytes/m-p/1271994#M10779</link>
    <description>&lt;P&gt;Controller used : S32K344&lt;/P&gt;&lt;P&gt;I want to send (transmit) data via UART (DMA method) and also ensure that there is a time gap between each byte that is placed in the DATA register. I want to configure the whole data block in DMA initially and let DMA place each byte after a time interval.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Is there a way to ensure that there is a time gap between each byte that DMA places in the DATA register.?&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Wed, 05 May 2021 04:42:37 GMT</pubDate>
    <dc:creator>jjjopaul</dc:creator>
    <dc:date>2021-05-05T04:42:37Z</dc:date>
    <item>
      <title>UART DMA (time gap between bytes)</title>
      <link>https://community.nxp.com/t5/S32K/UART-DMA-time-gap-between-bytes/m-p/1271994#M10779</link>
      <description>&lt;P&gt;Controller used : S32K344&lt;/P&gt;&lt;P&gt;I want to send (transmit) data via UART (DMA method) and also ensure that there is a time gap between each byte that is placed in the DATA register. I want to configure the whole data block in DMA initially and let DMA place each byte after a time interval.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Is there a way to ensure that there is a time gap between each byte that DMA places in the DATA register.?&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 05 May 2021 04:42:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/UART-DMA-time-gap-between-bytes/m-p/1271994#M10779</guid>
      <dc:creator>jjjopaul</dc:creator>
      <dc:date>2021-05-05T04:42:37Z</dc:date>
    </item>
    <item>
      <title>Re: UART DMA (time gap between bytes)</title>
      <link>https://community.nxp.com/t5/S32K/UART-DMA-time-gap-between-bytes/m-p/1272148#M10785</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;yes, DMA supports periodic triggering by PIT.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="lukaszadrapa_0-1620213907216.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/143943iCC4FB41DAF2D1E8B/image-size/medium?v=v2&amp;amp;px=400" role="button" title="lukaszadrapa_0-1620213907216.png" alt="lukaszadrapa_0-1620213907216.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;Notice that the configuration above is hardwired. Only DMA channels 0-3 can be used for this feature and corresponding PIT channel needs to be configured. So, if you want to trigger DMA channel 0, only PIT 0 can be used.&lt;/P&gt;
&lt;P&gt;Take a look at "17.4.1 DMA channels with periodic triggering capability" for more details. The feature can be enabled by TRIG bit in DMAMUX channel configuration register.&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Lukas&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 05 May 2021 11:29:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/UART-DMA-time-gap-between-bytes/m-p/1272148#M10785</guid>
      <dc:creator>lukaszadrapa</dc:creator>
      <dc:date>2021-05-05T11:29:56Z</dc:date>
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