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    <title>topic A53 Core shutdown request in S32G</title>
    <link>https://community.nxp.com/t5/S32G/A53-Core-shutdown-request/m-p/1922941#M9769</link>
    <description>&lt;P&gt;Hello ,&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Board: S32G399RDB3 with Autosar application in M7 core ,and BSP.V.41 used in the A core&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Package:GoldVIP-S32G3-1.11.0&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;We are trying to shutdown A53_0 from master core(M7_0) and found this related link from NXP community&amp;nbsp;&amp;nbsp;&lt;A href="https://community.nxp.com/t5/S32G/M7-core-will-shutdown-A53-core-after-that-all-peripherals-has/m-p/1623235" target="_blank"&gt;M7 core will shutdown A53 core, after that all peripherals has disabled (CAN) why? - NXP Community&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;1.In that they are mentioning a shut down request from M core to A core ,So I would like to understand how this request&amp;nbsp; sent from M core and how it need to be handled ibn both M core and A core&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Thu, 01 Aug 2024 11:05:26 GMT</pubDate>
    <dc:creator>kavyapk</dc:creator>
    <dc:date>2024-08-01T11:05:26Z</dc:date>
    <item>
      <title>A53 Core shutdown request</title>
      <link>https://community.nxp.com/t5/S32G/A53-Core-shutdown-request/m-p/1922941#M9769</link>
      <description>&lt;P&gt;Hello ,&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Board: S32G399RDB3 with Autosar application in M7 core ,and BSP.V.41 used in the A core&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Package:GoldVIP-S32G3-1.11.0&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;We are trying to shutdown A53_0 from master core(M7_0) and found this related link from NXP community&amp;nbsp;&amp;nbsp;&lt;A href="https://community.nxp.com/t5/S32G/M7-core-will-shutdown-A53-core-after-that-all-peripherals-has/m-p/1623235" target="_blank"&gt;M7 core will shutdown A53 core, after that all peripherals has disabled (CAN) why? - NXP Community&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;1.In that they are mentioning a shut down request from M core to A core ,So I would like to understand how this request&amp;nbsp; sent from M core and how it need to be handled ibn both M core and A core&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 01 Aug 2024 11:05:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/A53-Core-shutdown-request/m-p/1922941#M9769</guid>
      <dc:creator>kavyapk</dc:creator>
      <dc:date>2024-08-01T11:05:26Z</dc:date>
    </item>
    <item>
      <title>Re: A53 Core shutdown request</title>
      <link>https://community.nxp.com/t5/S32G/A53-Core-shutdown-request/m-p/1923107#M9774</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;For the available information, we understand that there is no official documentation from NXP on this regard. We do apologize.&lt;/P&gt;
&lt;P&gt;We can recommend opening a case under the NXP online services or contacting your local NXP FAE/DFAE/representative to understand if there are any steps available. Again, we do apologize.&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
      <pubDate>Thu, 01 Aug 2024 14:56:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/A53-Core-shutdown-request/m-p/1923107#M9774</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2024-08-01T14:56:54Z</dc:date>
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