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    <title>topic S32G2: TCM Backdoor memory not accessible in S32G</title>
    <link>https://community.nxp.com/t5/S32G/S32G2-TCM-Backdoor-memory-not-accessible/m-p/1919558#M9680</link>
    <description>&lt;P&gt;Accoring the manual the each TCM has a backdoor address, e.g. TCM-Core0 should be at 0x2010.0000.&lt;/P&gt;&lt;P&gt;But there is no memory at all.&lt;/P&gt;&lt;P&gt;I cannot find info on how to enable the backdoor access?&lt;/P&gt;&lt;P&gt;Maybe anyone has a pointer where to look at.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Related: Standby SRAM (0x2400.0000) is not accessible as well.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Cheers&lt;/P&gt;&lt;P&gt;42Bastian&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Mon, 29 Jul 2024 15:31:50 GMT</pubDate>
    <dc:creator>bastian_schick</dc:creator>
    <dc:date>2024-07-29T15:31:50Z</dc:date>
    <item>
      <title>S32G2: TCM Backdoor memory not accessible</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-TCM-Backdoor-memory-not-accessible/m-p/1919558#M9680</link>
      <description>&lt;P&gt;Accoring the manual the each TCM has a backdoor address, e.g. TCM-Core0 should be at 0x2010.0000.&lt;/P&gt;&lt;P&gt;But there is no memory at all.&lt;/P&gt;&lt;P&gt;I cannot find info on how to enable the backdoor access?&lt;/P&gt;&lt;P&gt;Maybe anyone has a pointer where to look at.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Related: Standby SRAM (0x2400.0000) is not accessible as well.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Cheers&lt;/P&gt;&lt;P&gt;42Bastian&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 29 Jul 2024 15:31:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-TCM-Backdoor-memory-not-accessible/m-p/1919558#M9680</guid>
      <dc:creator>bastian_schick</dc:creator>
      <dc:date>2024-07-29T15:31:50Z</dc:date>
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    <item>
      <title>Re: S32G2: TCM Backdoor memory not accessible</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-TCM-Backdoor-memory-not-accessible/m-p/1920593#M9721</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;On regards of the TCM Backdoor, the following is told:&lt;/P&gt;
&lt;P&gt;"&lt;SPAN&gt;M7 cores cannot access any TCM through backdoor ports. Except M7 cores, the other bus masters, e.g. A53 cores, DMA etc., can access the respective TCMs via backdoor ports. &lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;In other words, M7 can only access its own TCM through TCM port bus and cannot access other M7’s TCM. Non-M7 bus masters can access all M7’s TCMs through respective backdoor ports.&lt;/SPAN&gt;"&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
      <pubDate>Tue, 30 Jul 2024 14:27:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-TCM-Backdoor-memory-not-accessible/m-p/1920593#M9721</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2024-07-30T14:27:29Z</dc:date>
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    <item>
      <title>Re: S32G2: TCM Backdoor memory not accessible</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-TCM-Backdoor-memory-not-accessible/m-p/1920598#M9724</link>
      <description>&lt;P&gt;Thanks for clarification. Such should be noted fat in the manual.&lt;/P&gt;&lt;P&gt;I assume this applies to Standby SRAM as well? Or"shared HSE" RAM?&lt;/P&gt;&lt;P&gt;So only DDRAM or "general" SRAM can be used to exchange data between CM7 cores, right?&lt;/P&gt;</description>
      <pubDate>Tue, 30 Jul 2024 14:34:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-TCM-Backdoor-memory-not-accessible/m-p/1920598#M9724</guid>
      <dc:creator>bastian_schick</dc:creator>
      <dc:date>2024-07-30T14:34:59Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2: TCM Backdoor memory not accessible</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-TCM-Backdoor-memory-not-accessible/m-p/1920867#M9738</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;Thanks for your feedback. For core-to-core communication, seems to be that it is as you say. You should also be able to use the IPCF package (link to product page:&amp;nbsp;&lt;A href="https://www.nxp.com/design/design-center/software/automotive-software-and-tools/inter-platform-communication-framework-ipcf:IPCF" target="_blank"&gt;Inter-Platform Communication Framework (IPCF) | NXP Semiconductors&lt;/A&gt;) which is a framework for core-to-core communication.&lt;/P&gt;
&lt;P&gt;Please, let us know.&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 30 Jul 2024 20:59:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-TCM-Backdoor-memory-not-accessible/m-p/1920867#M9738</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2024-07-30T20:59:31Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2: TCM Backdoor memory not accessible</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-TCM-Backdoor-memory-not-accessible/m-p/1921192#M9743</link>
      <description>SCIOPTA Core2Core communication uses a slimlined technic as part of the kernel and does not rely on a any 3rd party framework. But I need to know which core can read/write which memory. A pity that in the S32K3 TCM backdoors are readable but in S32G not. (Design fault or wanted?)&lt;BR /&gt;Anyway thx for clarification.</description>
      <pubDate>Wed, 31 Jul 2024 05:33:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-TCM-Backdoor-memory-not-accessible/m-p/1921192#M9743</guid>
      <dc:creator>bastian_schick</dc:creator>
      <dc:date>2024-07-31T05:33:05Z</dc:date>
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