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    <title>S32GのトピックRe: Enabling CoreSight on S32G2</title>
    <link>https://community.nxp.com/t5/S32G/Enabling-CoreSight-on-S32G2/m-p/1914320#M9130</link>
    <description>&lt;P&gt;&lt;SPAN&gt;Hi,&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;As to this moment, we understand that the c&lt;/SPAN&gt;&lt;SPAN&gt;urrent BSP software does not support coresight, and no plans to support it in a short term.&lt;/SPAN&gt;&lt;BR clear="none" /&gt;&lt;BR clear="none" /&gt;&lt;SPAN&gt;All the available features for the BSP version you are using should be provided in the "Linux BSP vxx.x User Manual", given CoreSight is not mentioned as a feature, there is no explanation on enablement.&lt;/SPAN&gt;&lt;BR clear="none" /&gt;&lt;BR clear="none" /&gt;&lt;SPAN&gt;We do apologize for this inconvenience.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Please let us know.&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Mon, 22 Jul 2024 16:40:27 GMT</pubDate>
    <dc:creator>Daniel-Aguirre</dc:creator>
    <dc:date>2024-07-22T16:40:27Z</dc:date>
    <item>
      <title>Enabling CoreSight on S32G2</title>
      <link>https://community.nxp.com/t5/S32G/Enabling-CoreSight-on-S32G2/m-p/1914060#M9079</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;We are trying to enable CoreSight for hardware assisted tracing on S32G-VNP-RDB2 running a Linux BSP 38.0 build.&lt;BR /&gt;Although compiling the kernel with CoreSight features enabled adds the required modules, there are no CoreSight devices available in '/sys/bus/coresight/devices/'.&lt;BR /&gt;Looking at the used device tree configuration, it doesn't contain any CoreSight components.&lt;BR /&gt;Can someone provide us with an updated device tree configuration file or recommend a compatible platform we can use as a base to implement the changes ourselves?&lt;/P&gt;&lt;P&gt;Thank you in advance.&lt;/P&gt;</description>
      <pubDate>Mon, 22 Jul 2024 11:46:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Enabling-CoreSight-on-S32G2/m-p/1914060#M9079</guid>
      <dc:creator>Marin</dc:creator>
      <dc:date>2024-07-22T11:46:01Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling CoreSight on S32G2</title>
      <link>https://community.nxp.com/t5/S32G/Enabling-CoreSight-on-S32G2/m-p/1914320#M9130</link>
      <description>&lt;P&gt;&lt;SPAN&gt;Hi,&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;As to this moment, we understand that the c&lt;/SPAN&gt;&lt;SPAN&gt;urrent BSP software does not support coresight, and no plans to support it in a short term.&lt;/SPAN&gt;&lt;BR clear="none" /&gt;&lt;BR clear="none" /&gt;&lt;SPAN&gt;All the available features for the BSP version you are using should be provided in the "Linux BSP vxx.x User Manual", given CoreSight is not mentioned as a feature, there is no explanation on enablement.&lt;/SPAN&gt;&lt;BR clear="none" /&gt;&lt;BR clear="none" /&gt;&lt;SPAN&gt;We do apologize for this inconvenience.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Please let us know.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 22 Jul 2024 16:40:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Enabling-CoreSight-on-S32G2/m-p/1914320#M9130</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2024-07-22T16:40:27Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling CoreSight on S32G2</title>
      <link>https://community.nxp.com/t5/S32G/Enabling-CoreSight-on-S32G2/m-p/1927217#M9990</link>
      <description>&lt;DIV&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/205137"&gt;@Daniel-Aguirre&lt;/a&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;we are trying to do this for the S32G3 based on the BSP-41.&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;I was able to extend the dtsi tree with the etms, funnels, etrs.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;find . -name "*etm*&lt;/DIV&gt;&lt;DIV&gt;./usr/bin/setmetamode&lt;/DIV&gt;&lt;DIV&gt;./lib/modules/5.15.153-rt75+gadceb7e8fa72/kernel/drivers/hwtracing/coresight/coresight-etm4x.ko&lt;/DIV&gt;&lt;DIV&gt;./sys/class/devlink/platform:firmware:scmi--amba:51440000.etm&lt;/DIV&gt;&lt;DIV&gt;./sys/class/devlink/platform:firmware:scmi--amba:51540000.etm&lt;/DIV&gt;&lt;DIV&gt;./sys/class/devlink/platform:firmware:scmi--amba:51640000.etm&lt;/DIV&gt;&lt;DIV&gt;./sys/class/devlink/platform:firmware:scmi--amba:51740000.etm&lt;/DIV&gt;&lt;DIV&gt;./sys/devices/platform/51440000.etm&lt;/DIV&gt;&lt;DIV&gt;./sys/devices/platform/51540000.etm&lt;/DIV&gt;&lt;DIV&gt;./sys/devices/platform/51640000.etm&lt;/DIV&gt;&lt;DIV&gt;./sys/devices/platform/51740000.etm&lt;/DIV&gt;&lt;DIV&gt;./sys/devices/platform/firmware:scmi/consumer:amba:51740000.etm&lt;/DIV&gt;&lt;DIV&gt;./sys/devices/platform/firmware:scmi/consumer:amba:51440000.etm&lt;/DIV&gt;&lt;DIV&gt;./sys/devices/platform/firmware:scmi/consumer:amba:51540000.etm&lt;/DIV&gt;&lt;DIV&gt;./sys/devices/platform/firmware:scmi/consumer:amba:51640000.etm&lt;/DIV&gt;&lt;DIV&gt;./sys/devices/cs_etm&lt;/DIV&gt;&lt;DIV&gt;./sys/devices/virtual/devlink/platform:firmware:scmi--amba:51440000.etm&lt;/DIV&gt;&lt;DIV&gt;./sys/devices/virtual/devlink/platform:firmware:scmi--amba:51540000.etm&lt;/DIV&gt;&lt;DIV&gt;./sys/devices/virtual/devlink/platform:firmware:scmi--amba:51640000.etm&lt;/DIV&gt;&lt;DIV&gt;./sys/devices/virtual/devlink/platform:firmware:scmi--amba:51740000.etm&lt;/DIV&gt;&lt;DIV&gt;./sys/bus/amba/devices/51440000.etm&lt;/DIV&gt;&lt;DIV&gt;./sys/bus/amba/devices/51540000.etm&lt;/DIV&gt;&lt;DIV&gt;./sys/bus/amba/devices/51640000.etm&lt;/DIV&gt;&lt;DIV&gt;./sys/bus/amba/devices/51740000.etm&lt;/DIV&gt;&lt;DIV&gt;./sys/bus/amba/drivers/coresight-etm4x&lt;/DIV&gt;&lt;DIV&gt;./sys/bus/platform/drivers/coresight-etm4x&lt;/DIV&gt;&lt;DIV&gt;./sys/bus/event_source/devices/cs_etm&lt;/DIV&gt;&lt;DIV&gt;./sys/firmware/devicetree/base/etm@51740000&lt;/DIV&gt;&lt;DIV&gt;./sys/firmware/devicetree/base/etm@51640000&lt;/DIV&gt;&lt;DIV&gt;./sys/firmware/devicetree/base/etm@51540000&lt;/DIV&gt;&lt;DIV&gt;./sys/firmware/devicetree/base/etm@51440000&lt;/DIV&gt;&lt;DIV&gt;./sys/module/coresight/holders/coresight_etm4x&lt;/DIV&gt;&lt;DIV&gt;./sys/module/coresight_etm4x&lt;/DIV&gt;&lt;DIV&gt;./sys/module/coresight_etm4x/drivers/platform:coresight-etm4x&lt;/DIV&gt;&lt;DIV&gt;./sys/module/coresight_etm4x/drivers/amba:coresight-etm4x&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;but unfortunately I cannot see any device running on the coresight bus.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;ls -la /sys/bus/coresight/devices/&lt;/DIV&gt;&lt;DIV&gt;total 0&lt;/DIV&gt;&lt;DIV&gt;drwxr-xr-x 2 root root 0 Apr 28 18:53 .&lt;/DIV&gt;&lt;DIV&gt;drwxr-xr-x 4 root root 0 Apr 28 17:42 ..&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;The etms, funnels, etrs are enabled in the device tree:&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;status = "okay";&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;What is unclear in the documentation (reference manual S32G3) is what clocks should be used for the CoreSight and each of the devices?&lt;/DIV&gt;&lt;DIV&gt;RM mentions in the chapter 77.6.1 that the clocks used are sys2_clk and core2_clk, but these are nowhere described that they are. Can you please provide information what clocks these are? and how the following should be configured&lt;/DIV&gt;&lt;DIV&gt;cpu = &amp;lt;&amp;amp;clks&amp;gt;;&lt;/DIV&gt;&lt;DIV&gt;clocks = &amp;lt;&amp;amp;clks S32G_SCMI_CLK_PFE_AXI&amp;gt;; //Find a correct clock - core2_clk&lt;/DIV&gt;&lt;DIV&gt;clock-names = "core2_clk"; //Find a correct clock - core2_clk&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Thank you for the support.&amp;nbsp;&lt;/DIV&gt;</description>
      <pubDate>Wed, 07 Aug 2024 09:12:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Enabling-CoreSight-on-S32G2/m-p/1927217#M9990</guid>
      <dc:creator>Miodrag</dc:creator>
      <dc:date>2024-08-07T09:12:10Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling CoreSight on S32G2</title>
      <link>https://community.nxp.com/t5/S32G/Enabling-CoreSight-on-S32G2/m-p/1927235#M9991</link>
      <description>PS: we enabled the coresight features in the kernel menuconfig.</description>
      <pubDate>Wed, 07 Aug 2024 09:30:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Enabling-CoreSight-on-S32G2/m-p/1927235#M9991</guid>
      <dc:creator>Miodrag</dc:creator>
      <dc:date>2024-08-07T09:30:57Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling CoreSight on S32G2</title>
      <link>https://community.nxp.com/t5/S32G/Enabling-CoreSight-on-S32G2/m-p/1928331#M10015</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;Thanks for your feedback. As told before, a&lt;SPAN&gt;ll the available features for the BSP version you are using should be provided in the "Linux BSP 41.0 User Manual", given CoreSight is not mentioned as a feature, there is no explanation on enablement. We do apologize.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;We can recommend contacting your local NXP FAE/DFAE/representative, for them to channel this request adequately.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Again, we do apologize.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Please, let us know.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 08 Aug 2024 14:23:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Enabling-CoreSight-on-S32G2/m-p/1928331#M10015</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2024-08-08T14:23:37Z</dc:date>
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