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    <title>S32G中的主题 Re: S32G2 ETHERNET MUXING</title>
    <link>https://community.nxp.com/t5/S32G/S32G2-ETHERNET-MUXING/m-p/1894308#M7340</link>
    <description>&lt;P&gt;Is there any update?&lt;/P&gt;</description>
    <pubDate>Wed, 26 Jun 2024 09:57:53 GMT</pubDate>
    <dc:creator>JasonTseng</dc:creator>
    <dc:date>2024-06-26T09:57:53Z</dc:date>
    <item>
      <title>S32G2 ETHERNET MUXING</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-ETHERNET-MUXING/m-p/1890189#M7270</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;Please check p. 10 from below link&lt;/P&gt;&lt;P&gt;&lt;A href="https://www.nxp.com/design/training/understanding-the-s32g2-ethernet-architecture:TIP-UNDERSTANDING-THE-S32G2-ETHERNET-ARCHITECTURE" target="_blank"&gt;https://www.nxp.com/design/training/understanding-the-s32g2-ethernet-architecture:TIP-UNDERSTANDING-THE-S32G2-ETHERNET-ARCHITECTURE&lt;/A&gt;&lt;/P&gt;&lt;P&gt;Q1:&amp;nbsp;S32G2 525FC BGA supports:&amp;nbsp;Max of 3X RGMII/RMII/MII* interfaces (mux options available for all MACs). There are 4 gmac in S32G2 totally, which one of them cannot be&amp;nbsp;RGMII/RMII/MII* interface? and why?&lt;/P&gt;&lt;P&gt;Q2: there is a statement "Each RGMII additionally supports RMII &amp;amp; MII&lt;BR /&gt;(*MII requires additional mux signals in LLCE)". which additional mux signal is needed for MII? and why?&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;</description>
      <pubDate>Wed, 19 Jun 2024 08:25:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-ETHERNET-MUXING/m-p/1890189#M7270</guid>
      <dc:creator>JasonTseng</dc:creator>
      <dc:date>2024-06-19T08:25:28Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2 ETHERNET MUXING</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-ETHERNET-MUXING/m-p/1891502#M7284</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;Please check:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/Direct-ETH-MAC-MII-to-MAC-MII-connection/m-p/1042795" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors/Direct-ETH-MAC-MII-to-MAC-MII-connection/m-p/1042795&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Is for i.MX but it can help&lt;/P&gt;
&lt;P&gt;Regards&lt;/P&gt;</description>
      <pubDate>Thu, 20 Jun 2024 14:54:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-ETHERNET-MUXING/m-p/1891502#M7284</guid>
      <dc:creator>Bio_TICFSL</dc:creator>
      <dc:date>2024-06-20T14:54:45Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2 ETHERNET MUXING</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-ETHERNET-MUXING/m-p/1891753#M7288</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I read the link you provided, but it doesn't provide any help with my two questions.&lt;/P&gt;&lt;P&gt;Please provide more specific answers.&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;</description>
      <pubDate>Fri, 21 Jun 2024 01:52:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-ETHERNET-MUXING/m-p/1891753#M7288</guid>
      <dc:creator>JasonTseng</dc:creator>
      <dc:date>2024-06-21T01:52:09Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2 ETHERNET MUXING</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-ETHERNET-MUXING/m-p/1894308#M7340</link>
      <description>&lt;P&gt;Is there any update?&lt;/P&gt;</description>
      <pubDate>Wed, 26 Jun 2024 09:57:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-ETHERNET-MUXING/m-p/1894308#M7340</guid>
      <dc:creator>JasonTseng</dc:creator>
      <dc:date>2024-06-26T09:57:53Z</dc:date>
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