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    <title>topic Re: will RESET_B cause S32G to enter function reset sequence? in S32G</title>
    <link>https://community.nxp.com/t5/S32G/will-RESET-B-cause-S32G-to-enter-function-reset-sequence/m-p/1881560#M7166</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;On regards of RESET_B functionality, the following is told under the S32G2 RM [Page 1145, S32G2 Reference Manual, Rev. 8, February 2024]:&lt;/P&gt;
&lt;P&gt;"&lt;/P&gt;
&lt;P&gt;The default configuration, which is set immediately on destructive and power-on reset sequence entries, is that all functional reset&lt;BR /&gt;events cause RESET_B to be asserted.&lt;/P&gt;
&lt;P&gt;...&lt;/P&gt;
&lt;P&gt;The RESET_B pin is asserted by the off-chip power management circuitry starting before the device supplies begin ramping&lt;BR /&gt;up and at least until the POR_B pin is deasserted. This prevents the RESET_B pin from behaving erratically when its supply is&lt;BR /&gt;ramping up.&lt;/P&gt;
&lt;P&gt;"&lt;/P&gt;
&lt;P&gt;Which at the end, this signal should be handled by the off-chip PMIC.&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
    <pubDate>Wed, 05 Jun 2024 14:10:04 GMT</pubDate>
    <dc:creator>Daniel-Aguirre</dc:creator>
    <dc:date>2024-06-05T14:10:04Z</dc:date>
    <item>
      <title>will RESET_B cause S32G to enter function reset sequence?</title>
      <link>https://community.nxp.com/t5/S32G/will-RESET-B-cause-S32G-to-enter-function-reset-sequence/m-p/1881397#M7156</link>
      <description>&lt;P&gt;Hi&amp;nbsp; all,&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; In the S32G2 RM, it's said as follows. Is the RESET_B input only for DEBUG? Does the RESET_B input cause S32G to&amp;nbsp;enter function reset sequence? What's the meaning of DEBUG here?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="brian_w_0-1717578015540.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/282591i58B72AD6D0ECB79A/image-size/medium?v=v2&amp;amp;px=400" role="button" title="brian_w_0-1717578015540.png" alt="brian_w_0-1717578015540.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 05 Jun 2024 09:01:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/will-RESET-B-cause-S32G-to-enter-function-reset-sequence/m-p/1881397#M7156</guid>
      <dc:creator>brian_w</dc:creator>
      <dc:date>2024-06-05T09:01:30Z</dc:date>
    </item>
    <item>
      <title>Re: will RESET_B cause S32G to enter function reset sequence?</title>
      <link>https://community.nxp.com/t5/S32G/will-RESET-B-cause-S32G-to-enter-function-reset-sequence/m-p/1881560#M7166</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;On regards of RESET_B functionality, the following is told under the S32G2 RM [Page 1145, S32G2 Reference Manual, Rev. 8, February 2024]:&lt;/P&gt;
&lt;P&gt;"&lt;/P&gt;
&lt;P&gt;The default configuration, which is set immediately on destructive and power-on reset sequence entries, is that all functional reset&lt;BR /&gt;events cause RESET_B to be asserted.&lt;/P&gt;
&lt;P&gt;...&lt;/P&gt;
&lt;P&gt;The RESET_B pin is asserted by the off-chip power management circuitry starting before the device supplies begin ramping&lt;BR /&gt;up and at least until the POR_B pin is deasserted. This prevents the RESET_B pin from behaving erratically when its supply is&lt;BR /&gt;ramping up.&lt;/P&gt;
&lt;P&gt;"&lt;/P&gt;
&lt;P&gt;Which at the end, this signal should be handled by the off-chip PMIC.&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
      <pubDate>Wed, 05 Jun 2024 14:10:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/will-RESET-B-cause-S32G-to-enter-function-reset-sequence/m-p/1881560#M7166</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2024-06-05T14:10:04Z</dc:date>
    </item>
    <item>
      <title>Re: will RESET_B cause S32G to enter function reset sequence?</title>
      <link>https://community.nxp.com/t5/S32G/will-RESET-B-cause-S32G-to-enter-function-reset-sequence/m-p/1882151#M7174</link>
      <description>&lt;P&gt;Hi Daniel,&lt;/P&gt;&lt;P&gt;Thanks a lot.&lt;/P&gt;&lt;P&gt;As you say, the RESET_B will reset S32G, but why the table that I quote says that the RESET_B is intended to be used for debug only?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;H1&gt;&amp;nbsp;&lt;/H1&gt;&lt;H1&gt;&amp;nbsp;&lt;/H1&gt;</description>
      <pubDate>Thu, 06 Jun 2024 01:03:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/will-RESET-B-cause-S32G-to-enter-function-reset-sequence/m-p/1882151#M7174</guid>
      <dc:creator>brian_w</dc:creator>
      <dc:date>2024-06-06T01:03:42Z</dc:date>
    </item>
    <item>
      <title>Re: will RESET_B cause S32G to enter function reset sequence?</title>
      <link>https://community.nxp.com/t5/S32G/will-RESET-B-cause-S32G-to-enter-function-reset-sequence/m-p/1882800#M7181</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;For what we are able to understand, seems related to the internal reset state machine of S32G.&lt;/P&gt;
&lt;P&gt;Since the internal state machine will internally assert this signal, it seems to tell that it is for debugging as if it should only be used under debug purposes, but not to initiate a Functional Reset.&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
      <pubDate>Thu, 06 Jun 2024 13:58:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/will-RESET-B-cause-S32G-to-enter-function-reset-sequence/m-p/1882800#M7181</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2024-06-06T13:58:01Z</dc:date>
    </item>
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