topic Re: S32G274A Internal RAM No Cacheable in S32G

S32G274A Internal RAM No Cacheable

Vishnu3 — Fri, 31 May 2024 15:47:50 GMT

Hello,

I have been working with S32G274A processor. I have been working on a bootloader and the default RAM configuration are as follows in the linker file:

int_sram                : ORIGIN = 0x34000000, LENGTH = 0x00080000 /* 512KB */

int_sram_stack_c0       : ORIGIN = 0x34080000, LENGTH = 0x00002000 /* 8KB */
int_sram_stack_c1       : ORIGIN = 0x34082000, LENGTH = 0x00002000 /* 8KB */
int_sram_stack_c2       : ORIGIN = 0x34084000, LENGTH = 0x00002000 /* 8KB */

// Non Cacheable

int_sram_no_cacheable : ORIGIN = 0x34500000, LENGTH = 0x00100000

I reduced the sram size to 512 Kb but the sram no cacheable starts at 0x34500000 and my bootloader blows up to 5MB. It is difficult for me to allocate application image space in between. So I reconfigured the no cacheable address to 0x34100000 with 1 MB length and made the same changes in the RM module in the peripherals. I got this working and the total bootloader size was around ~ 1.2 MB. However, when I added some more code to my existing bootloader it crashed again and the SRAM no cacheable memory start address only accepts 0x34500000. If not this address it crashes. How do I properly change this no cacheable address so that I have a compact bootloader of around 2MB and can dedicate rest of the RAM space (~6 MB) for application space. I want to have continuous memory configuration.

Best,

Vishnu

Re: S32G274A Internal RAM No Cacheable

Daniel-Aguirre — Mon, 03 Jun 2024 14:04:39 GMT

Hi,

Did you configure the MPU? If not, this situation could be related to the MPU default configurations. The following is told by the internal team:

S32DS project uses the default MPU configurations defined in core_specific.h through the array rbar[] and array rasr[], regardless of the memory region descriptions in linker_ram.ld.

For RTD4.4.3(D2112) project, the file path of core_specific.h is generally C:\NXP\S32DS.3.4\S32DS\software\PlatformSDK_S32XX_2021_12\SW32_RTD_4_4_3_0_0_D2112\Platform_TS_T40D11M30I0R0\startup\include\ core_specific.h.

The changing in linker_ram.ld will be effective for image building but will not change the parameters for MPU configurations.

Please, let us know.

Re: S32G274A Internal RAM No Cacheable

Vishnu3 — Mon, 03 Jun 2024 17:45:46 GMT

Hi Daniel,

Thank you for the response, I was able to figure this out. Now I am wondering how do I make these changes in the best way possible. The core_specific.h file is a file that is shared by all my projects, so where must I make the changes for the RBAR? Should I define them accordingly in the system.c file itself? Also, shouldn't configuring the RM module in the peripherals GUI automatically take care of this? Making changes in code like this is quite cumbersome.

Best,

Vishnu

Re: S32G274A Internal RAM No Cacheable

Daniel-Aguirre — Mon, 03 Jun 2024 20:37:19 GMT

Hi,

In general, are you using the MPU or not? If you are not planning on using the MPU, you should be able to disable it.

As for the changes, these are the default configs. If you are using the MPU, you should configure it under Config Tools then initialize it.

As for the Rm (which we assume it is XRDC), it does not configure the MPU. It will create domains and assign permits, but it is no MPU.

Please, let us know.

Re: S32G274A Internal RAM No Cacheable

Vishnu3 — Tue, 04 Jun 2024 05:29:15 GMT

Thank you for that info. Where can I configure MPU in the config tools? Please let me know.

Best,

Vishnu

Re: S32G274A Internal RAM No Cacheable

Vishnu3 — Tue, 04 Jun 2024 05:43:26 GMT

I am configuring the MPU_M7 under the RM, not XRDC. I think I am not initializing it properly. How can this be achieved?

Re: S32G274A Internal RAM No Cacheable

Daniel-Aguirre — Tue, 04 Jun 2024 13:01:55 GMT

Hi,

Thanks for your feedback. Are you using any NXP example? If not, can you reproduce the behavior under an NXP example?

In which RTD version are you working on?

We understand that, if configured correctly, the Rm_Init function should configure the MPU itself:

Please, let us know.