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    <title>S32G中的主题 Re: S32G2</title>
    <link>https://community.nxp.com/t5/S32G/S32G2/m-p/1867872#M6959</link>
    <description>&lt;P&gt;Hello, @&lt;A href="https://community.nxp.com/t5/user/viewprofilepage/user-id/211565" target="_blank"&gt;gopalakrishna&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Thanks for the question.&lt;/P&gt;
&lt;P&gt;As far as I know, the external reference clock for PCIe/sgmii is HCSL level on RDB2, you can refer to design files of the RDB2 for details.&lt;/P&gt;
&lt;P&gt;May I know if HCSL could also be accepted or have to be LP-HCSL ?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best Regards&lt;/P&gt;
&lt;P&gt;Chenyin&lt;/P&gt;</description>
    <pubDate>Fri, 17 May 2024 08:20:58 GMT</pubDate>
    <dc:creator>chenyin_h</dc:creator>
    <dc:date>2024-05-17T08:20:58Z</dc:date>
    <item>
      <title>S32G2</title>
      <link>https://community.nxp.com/t5/S32G/S32G2/m-p/1866824#M6920</link>
      <description>&lt;P&gt;In one of our application using the S32G2 NXP processor (Part Nr:&amp;nbsp;S32G254AABK1VUCT) and PCIe interface is using. A 100MHz (Clock freq configurable) external clock generator is interfaced for&amp;nbsp;PCIE1_CLK_P,&amp;nbsp;PCIE1_CLK_N signals.&lt;/P&gt;&lt;P&gt;Please confirm the clock type - LVDS/ LP-HSCL?&lt;/P&gt;&lt;P&gt;Thank you.&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Gopala&lt;/P&gt;</description>
      <pubDate>Thu, 16 May 2024 06:13:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2/m-p/1866824#M6920</guid>
      <dc:creator>gopalakrishna</dc:creator>
      <dc:date>2024-05-16T06:13:24Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2</title>
      <link>https://community.nxp.com/t5/S32G/S32G2/m-p/1867872#M6959</link>
      <description>&lt;P&gt;Hello, @&lt;A href="https://community.nxp.com/t5/user/viewprofilepage/user-id/211565" target="_blank"&gt;gopalakrishna&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Thanks for the question.&lt;/P&gt;
&lt;P&gt;As far as I know, the external reference clock for PCIe/sgmii is HCSL level on RDB2, you can refer to design files of the RDB2 for details.&lt;/P&gt;
&lt;P&gt;May I know if HCSL could also be accepted or have to be LP-HCSL ?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best Regards&lt;/P&gt;
&lt;P&gt;Chenyin&lt;/P&gt;</description>
      <pubDate>Fri, 17 May 2024 08:20:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2/m-p/1867872#M6959</guid>
      <dc:creator>chenyin_h</dc:creator>
      <dc:date>2024-05-17T08:20:58Z</dc:date>
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