topic Re: S32G pinouts in S32G

S32G pinouts

JasonTseng — Sat, 11 May 2024 23:49:41 GMT

Hello,

I may miss something but unfortunately I cannot find S32G pinout descriptions.

In datasheet, it mentioned "For package pinouts and signal descriptions, see device Reference Manual."

Does that mean "S32G3 Reference Manual" or "GMAC/Serdes Subsystem Reference Manual"?

But none of them include pinout descriptions.

I am looking for the mapping table between all symbols name / package type / I/O type / function number /pin description.

Thanks

Re: S32G pinouts

chenyin_h — Mon, 13 May 2024 10:17:59 GMT

Hello, @JasonTseng

Thanks for the questions.

You may open your S32G3 RM, then click on the attachments as the snapshot below: (captured from Adobe Reader 2024.001, may differ while using different tools)

Then you may find several xlsx files attached, S32G3_IOMUX file may be one of which you are looking for.

Hope it helps

Best Regards

Chenyin

Re: S32G pinouts

JasonTseng — Tue, 14 May 2024 02:24:44 GMT

Hello ChenYin,

Thanks for the information.

It is helpful but it seems still not complete.

For example the function of pin U19 should be PFE_MAC0_TXD0.

But in which doc I can find this information?

Thanks

Re: S32G pinouts

chenyin_h — Tue, 14 May 2024 09:12:38 GMT

Hello, @JasonTseng

Thanks for the feedback.

Not sure if you were referring to the function PFE_MAC0_TXD_O[0]？ Seems they are also described from the document.

Click on the Tab: IO signal table, Row 771, PJ_00/U19/ PFE_MAC0_TXD_O[0], may I know if this is the specific information you are looking for?

Best Regards

Chenyin

Re: S32G pinouts

JasonTseng — Tue, 14 May 2024 12:23:00 GMT

Hello ChenYin,

You are saying Row 773, right?

How about Y18? where can I find it?

Thanks

Re: S32G pinouts

chenyin_h — Wed, 15 May 2024 04:09:35 GMT

Hello, @JasonTseng

Thanks for the feedback.

Yes, you can also find the corresponding information for Y18 from the TAB: Misc with pin controls, which is also part of document we mentioned.（Row144 from mine）

Best Regards

Chenyin

Re: S32G pinouts

JasonTseng — Wed, 15 May 2024 09:18:30 GMT

Hello ChenYin,

Does below pic show PCIe1 L1 and PFE_MAC1_SGMII are mutex?

If yes, that means PCIE1_TX1_N and PFE_MAC1_TXD_O[0] are mutex, right?

But PCIE1_TX1_N is Y18, PFE_MAC1_TXD_O is T23.

Is there anything wrong?

Thanks

Re: S32G pinouts

JasonTseng — Thu, 16 May 2024 06:51:04 GMT

Hello ChenYin,

Now I understood what is going on.

The pic shows PFE_MAC1_SGMII which means SGMII_PFE_MAC1 not PFE_MAC1_TXD_O.

So both of PCIE1_TX1_N and SGMII_PFE_MAC1 are Y18.

Am I correct?

Thanks

Re: S32G pinouts

chenyin_h — Thu, 16 May 2024 07:48:49 GMT

Hello, @JasonTseng

Thanks for the feedback and sorry for the delay.

Yes, correct, they are functions of Y18, furthermore, the serdes function combinations are as follows:

For the detailed functions related with Serdes, you may also reference the 52.1.2 of S32g2 RM.

Best Regards

Chenyin

Re: S32G pinouts

JasonTseng — Thu, 16 May 2024 08:34:21 GMT

@chenyin_h , thanks for the update.

BTW, the pic shows "PCIe1 L1 / PFE_MAC1_SGMII -> SERDES S1 L0 (ENET AQR107)

Assuming

Q1: "PCIe1 L1" means PCIe1 Lane1, right?

Q2: "PFE_MAC1_SGMII" means SGMII (PFE MAC1), right?

Q3: "SERDES S1 L0" means serdes1 lane0, right?

If the answers are all correct, what is the setting in RM Table 405.
SerDes_0 working modes and Table 406 SerDes_1 working modes?

I cannot find the combination of PCIe1 lane 1 + SGMII (PFE_MAC1).

Thanks

Re: S32G pinouts

chenyin_h — Fri, 17 May 2024 03:50:36 GMT

Hello, @JasonTseng

Thanks for the feedback.

The pic you are referring to is only a block diagram, for actual connections, you may refer to the schematic of EVB for details.

Regarding to the combination, all combinations are listed in the tables mentioned from RM. There are not any other combinations.

Best Regards

Chenyin

Re: S32G pinouts

JasonTseng — Fri, 17 May 2024 08:00:45 GMT

Hello ChenYin,

Sorry, I don't understand.

Let me ask this question in another way.

in S32G-VNP-EVB-QSG.pdf p. 4

It shows "PCIe1 L1 / PFE_MAC1_SGMII -> SERDES S1 L0 (ENET AQR107)", so

Q1: "PCIe1 L1" means PCIe1 Lane1, right?

Q2: "PFE_MAC1_SGMII" means SGMII (PFE MAC1), right?

Q3: "SERDES S1 L0" means serdes1 lane0, right?

Thanks

Re: S32G pinouts

chenyin_h — Fri, 17 May 2024 10:18:20 GMT

Hello, @JasonTseng

Thanks for the feedback.

Regarding to your questions:

Q1: "PCIe1 L1" means PCIe1 Lane1, right?

[C.Y] Yes

Q2: "PFE_MAC1_SGMII" means SGMII (PFE MAC1), right?

[C.Y] Yes

Q3: "SERDES S1 L0" means serdes1 lane0, right?

[C.Y] Seems confusion here, since only SERDES1_LANE1 could be configure to SGMII_PFE_MAC1.

But from the schematic, the PCIe1_lane1(or call it Serdes1_lane1) connect to the SGMII PHY via the connector, while the corresponding pins on connector are called serdes1_xx0xx, this maybe one possible reason that it is written as “SERDES S1 L0 (ENET AQR107) after the yellow arrow.

Whatever, from my opinion, you may refer to the following chart from the EVB UG to understand the connection for Serdes.

Hope it helps.

Best Regards

Chenyin

Re: S32G pinouts

JasonTseng — Sat, 18 May 2024 02:31:30 GMT

Hello ChenYin,

Combined the information for QSG/UG/Sch, the conclusion of the link from s32g to SGMII port on platform board as below

S32G -> Y18 -> PCIE1_TXN1/SGMII_PFE_MAC1 -> processor board daughter card -> platform board daughter card -> SERDES_1_TX0N (serdes S1 L0) -> eth AQR107, Single-port, 10Gbps PHY -> SGMII eth port

Is that correct?

Thanks

Re: S32G pinouts

chenyin_h — Mon, 20 May 2024 02:38:39 GMT

Hello, @JasonTseng

Thanks for the feedback.

I agree with you.

Best Regards

Chenyin

Re: S32G pinouts

GAOW — Wed, 24 Dec 2025 07:14:55 GMT

HELLO ,i have the same question,can you tell me which document include the mapping table between all symbols name / package type / I/O type / function number /pin description.
Thanks!

Re: S32G pinouts

GAOW — Fri, 26 Dec 2025 06:45:27 GMT

IS HERE