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  <channel>
    <title>topic Re: Wakeup on CAN/CAN-FD App Note in S32G</title>
    <link>https://community.nxp.com/t5/S32G/Wakeup-on-CAN-CAN-FD-App-Note/m-p/1825377#M6216</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;For TJA1044 support, help us opening a ticket under the NXP online services, since these PHY's are not supported under the public community. We do apologize for the inconvenience.&lt;/P&gt;
&lt;P&gt;As for an application note talking about wake on CAN for S32G2 processor, we don't see any information. We do apologize. There is though some steps available that might be useful:&lt;/P&gt;
&lt;P&gt;"&lt;/P&gt;
&lt;P&gt;1. The CAN phy receives the remote wake-up frame&lt;BR /&gt;2. The CAN phy RXD pin outputs a low level.&lt;/P&gt;
&lt;P&gt;3. S32G LLCE_CANx_RX pin as the wake-up source to wake up S32G. (S32G LLCE_CANx_RXD connected to CAN PHY RXD pin)&lt;/P&gt;
&lt;P&gt;4. S32G makes the MODEB pin output high&lt;/P&gt;
&lt;P&gt;5. VR5510 wake-up and power supply on.&lt;/P&gt;
&lt;P&gt;6. S32G execution application&lt;/P&gt;
&lt;P&gt;"&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
    <pubDate>Mon, 11 Mar 2024 17:11:23 GMT</pubDate>
    <dc:creator>Daniel-Aguirre</dc:creator>
    <dc:date>2024-03-11T17:11:23Z</dc:date>
    <item>
      <title>Wakeup on CAN/CAN-FD App Note</title>
      <link>https://community.nxp.com/t5/S32G/Wakeup-on-CAN-CAN-FD-App-Note/m-p/1825301#M6212</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I am using an NXP TJA1044 as a CAN-FD transceiver for an S32G2.&amp;nbsp; I am trying to see if there's any existing app notes on how to implement wake up on CAN.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;--Jordan&lt;/P&gt;</description>
      <pubDate>Mon, 11 Mar 2024 15:16:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Wakeup-on-CAN-CAN-FD-App-Note/m-p/1825301#M6212</guid>
      <dc:creator>jmelnych_ford</dc:creator>
      <dc:date>2024-03-11T15:16:09Z</dc:date>
    </item>
    <item>
      <title>Re: Wakeup on CAN/CAN-FD App Note</title>
      <link>https://community.nxp.com/t5/S32G/Wakeup-on-CAN-CAN-FD-App-Note/m-p/1825377#M6216</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;For TJA1044 support, help us opening a ticket under the NXP online services, since these PHY's are not supported under the public community. We do apologize for the inconvenience.&lt;/P&gt;
&lt;P&gt;As for an application note talking about wake on CAN for S32G2 processor, we don't see any information. We do apologize. There is though some steps available that might be useful:&lt;/P&gt;
&lt;P&gt;"&lt;/P&gt;
&lt;P&gt;1. The CAN phy receives the remote wake-up frame&lt;BR /&gt;2. The CAN phy RXD pin outputs a low level.&lt;/P&gt;
&lt;P&gt;3. S32G LLCE_CANx_RX pin as the wake-up source to wake up S32G. (S32G LLCE_CANx_RXD connected to CAN PHY RXD pin)&lt;/P&gt;
&lt;P&gt;4. S32G makes the MODEB pin output high&lt;/P&gt;
&lt;P&gt;5. VR5510 wake-up and power supply on.&lt;/P&gt;
&lt;P&gt;6. S32G execution application&lt;/P&gt;
&lt;P&gt;"&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
      <pubDate>Mon, 11 Mar 2024 17:11:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Wakeup-on-CAN-CAN-FD-App-Note/m-p/1825377#M6216</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2024-03-11T17:11:23Z</dc:date>
    </item>
    <item>
      <title>Re: Wakeup on CAN/CAN-FD App Note</title>
      <link>https://community.nxp.com/t5/S32G/Wakeup-on-CAN-CAN-FD-App-Note/m-p/1826325#M6226</link>
      <description>&lt;P&gt;Thanks for the response Daniel,&lt;/P&gt;&lt;P&gt;I have the LLCE driver enabled for CAN.&amp;nbsp; Does that mean it should "just work" already or do I need to make any changes to the device tree or .config?&lt;/P&gt;</description>
      <pubDate>Tue, 12 Mar 2024 14:35:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Wakeup-on-CAN-CAN-FD-App-Note/m-p/1826325#M6226</guid>
      <dc:creator>jmelnych_ford</dc:creator>
      <dc:date>2024-03-12T14:35:35Z</dc:date>
    </item>
    <item>
      <title>Re: Wakeup on CAN/CAN-FD App Note</title>
      <link>https://community.nxp.com/t5/S32G/Wakeup-on-CAN-CAN-FD-App-Note/m-p/1826425#M6228</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;Thanks for your feedback. The LLCE-FW does not relate to the WKUP functionality of a specific pin. Since we understand that you are working with Linux (since you are mentioning the usage of a device tree), you should enable the WKUP functionality by adding the specific pin to the ATF device tree.&lt;/P&gt;
&lt;P&gt;Some steps should be shown under the specific BSP version User Manual. Below will be a capture of the BSP38.0 User Manual:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DanielAguirre_0-1710261099039.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/267911i7C0510C948100BBA/image-size/medium?v=v2&amp;amp;px=400" role="button" title="DanielAguirre_0-1710261099039.png" alt="DanielAguirre_0-1710261099039.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;This may vary from BSP version to BSP version, hence we recommend looking into your specific BSP version User Manual.&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
      <pubDate>Tue, 12 Mar 2024 16:33:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Wakeup-on-CAN-CAN-FD-App-Note/m-p/1826425#M6228</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2024-03-12T16:33:10Z</dc:date>
    </item>
    <item>
      <title>Re: Wakeup on CAN/CAN-FD App Note</title>
      <link>https://community.nxp.com/t5/S32G/Wakeup-on-CAN-CAN-FD-App-Note/m-p/1831282#M6322</link>
      <description>&lt;DIV class=""&gt;I made this modification (tried both `status="okay"` and `status="disabled"`) but was not able to stay asleep.&amp;nbsp;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class=""&gt;Snip of my modifications to arm-trusted-firmware s32cc.dtsi.&amp;nbsp; I tried both&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;status = "disabled"​ and&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;status = "okay"​&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;```&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; wkpu&lt;/SPAN&gt;&lt;SPAN&gt;: &lt;/SPAN&gt;&lt;SPAN&gt;wkpu@40090000&lt;/SPAN&gt;&lt;SPAN&gt; {&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;compatible = &lt;/SPAN&gt;&lt;SPAN&gt;"nxp,s32cc-wkpu"&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;reg = &amp;lt;&lt;/SPAN&gt;&lt;SPAN&gt;0x0&lt;/SPAN&gt; &lt;SPAN&gt;0x40090000&lt;/SPAN&gt; &lt;SPAN&gt;0x0&lt;/SPAN&gt; &lt;SPAN&gt;0x10000&lt;/SPAN&gt;&lt;SPAN&gt;&amp;gt;, &lt;/SPAN&gt;&lt;SPAN&gt;/* WKPU */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&amp;lt;&lt;/SPAN&gt;&lt;SPAN&gt;0x0&lt;/SPAN&gt; &lt;SPAN&gt;0x4007cb04&lt;/SPAN&gt; &lt;SPAN&gt;0x0&lt;/SPAN&gt; &lt;SPAN&gt;0x4&lt;/SPAN&gt;&lt;SPAN&gt;&amp;gt;; &lt;/SPAN&gt;&lt;SPAN&gt;/* S32G_STDBY_GPR */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;/*&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; * Enable RTC and GPIOs as wake-up source&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;nxp,irqs =&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&amp;lt;&lt;/SPAN&gt;&lt;SPAN&gt;S32GEN1_WKPU_RTC_IRQ&lt;/SPAN&gt; &lt;SPAN&gt;S32GEN1_WKPU_IRQ_RISING&lt;/SPAN&gt; &lt;SPAN&gt;S32GEN1_WKPU_PULL_DIS&lt;/SPAN&gt;&lt;SPAN&gt;&amp;gt;,&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&amp;lt;&lt;/SPAN&gt;&lt;SPAN&gt;S32GEN1_WKPU_EXT_IRQ&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;) &lt;/SPAN&gt;&lt;SPAN&gt;S32GEN1_WKPU_IRQ_FALLING&lt;/SPAN&gt; &lt;SPAN&gt;S32GEN1_WKPU_PULL_DIS&lt;/SPAN&gt;&lt;SPAN&gt;&amp;gt;, &lt;/SPAN&gt;&lt;SPAN&gt;/* PC_11 */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&amp;lt;&lt;/SPAN&gt;&lt;SPAN&gt;S32GEN1_WKPU_EXT_IRQ&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;1&lt;/SPAN&gt;&lt;SPAN&gt;) &lt;/SPAN&gt;&lt;SPAN&gt;S32GEN1_WKPU_IRQ_FALLING&lt;/SPAN&gt; &lt;SPAN&gt;S32GEN1_WKPU_PULL_DIS&lt;/SPAN&gt;&lt;SPAN&gt;&amp;gt;, &lt;/SPAN&gt;&lt;SPAN&gt;/* PJ_02 */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&amp;lt;&lt;/SPAN&gt;&lt;SPAN&gt;S32GEN1_WKPU_EXT_IRQ&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;2&lt;/SPAN&gt;&lt;SPAN&gt;) &lt;/SPAN&gt;&lt;SPAN&gt;S32GEN1_WKPU_IRQ_FALLING&lt;/SPAN&gt; &lt;SPAN&gt;S32GEN1_WKPU_PULL_DIS&lt;/SPAN&gt;&lt;SPAN&gt;&amp;gt;, &lt;/SPAN&gt;&lt;SPAN&gt;/* PJ_04 */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&amp;lt;&lt;/SPAN&gt;&lt;SPAN&gt;S32GEN1_WKPU_EXT_IRQ&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;4&lt;/SPAN&gt;&lt;SPAN&gt;) &lt;/SPAN&gt;&lt;SPAN&gt;S32GEN1_WKPU_IRQ_FALLING&lt;/SPAN&gt; &lt;SPAN&gt;S32GEN1_WKPU_PULL_DIS&lt;/SPAN&gt;&lt;SPAN&gt;&amp;gt;, &lt;/SPAN&gt;&lt;SPAN&gt;/* PJ_06 */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&amp;lt;&lt;/SPAN&gt;&lt;SPAN&gt;S32GEN1_WKPU_EXT_IRQ&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;9&lt;/SPAN&gt;&lt;SPAN&gt;) &lt;/SPAN&gt;&lt;SPAN&gt;S32GEN1_WKPU_IRQ_FALLING&lt;/SPAN&gt; &lt;SPAN&gt;S32GEN1_WKPU_PULL_DIS&lt;/SPAN&gt;&lt;SPAN&gt;&amp;gt;, &lt;/SPAN&gt;&lt;SPAN&gt;/* PK_02 */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&amp;lt;&lt;/SPAN&gt;&lt;SPAN&gt;S32GEN1_WKPU_EXT_IRQ&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;22&lt;/SPAN&gt;&lt;SPAN&gt;) &lt;/SPAN&gt;&lt;SPAN&gt;S32GEN1_WKPU_IRQ_FALLING&lt;/SPAN&gt; &lt;SPAN&gt;S32GEN1_WKPU_PULL_DIS&lt;/SPAN&gt;&lt;SPAN&gt;&amp;gt;; &lt;/SPAN&gt;&lt;SPAN&gt;/* PA_10 */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;nxp,warm-boot = &amp;lt;&lt;/SPAN&gt;&lt;SPAN&gt;S32GEN1_WKPU_LONG_BOOT&lt;/SPAN&gt;&lt;SPAN&gt;&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;status = &lt;/SPAN&gt;&lt;SPAN&gt;"okay"&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;};&lt;/DIV&gt;&lt;DIV&gt;```&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;Error that I get when trying to sleep (it's a little jumbled but it doesn't sleep and I get an i/o error)&lt;/DIV&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class=""&gt;```&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;P&gt;root@s32g274aucimdev1:/sys/devices/platform/soc/40060000.rtc/rtc/rtc0/power# echo mem &amp;gt; /sys/power/state&lt;BR /&gt;[ 294.077880] PM: suspend entry (deep)&lt;BR /&gt;[ 294.080347] Filesystems sync: 0.002 seconds&lt;BR /&gt;[ 294.081136] Freezing user space processes ... (elapsed 0.001 seconds) done.&lt;BR /&gt;[ 294.082458] OOM killer disabled.&lt;BR /&gt;[ 294.082462] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.&lt;BR /&gt;[ 294.083617] printk: Suspending console(s) (use no_console_suspend to debug)&lt;BR /&gt;[ 294.197500] pfeng 46000000.pfe: Suspending driver&lt;BR /&gt;[ 294.197866] pfeng 46000000.pfe pfe0: Link is Down&lt;BR /&gt;[ 294.197972] pfeng 46000000.pfe pfe0: Link is Up - 1Gbps/Full - flow control off&lt;BR /&gt;[ 294.198025] pfeng 46000000.pfe pfe0: Link is Down&lt;BR /&gt;[ 294.198427] pfeng 46000000.pfe pfe1: Link is Down&lt;BR /&gt;[ 294.198488] pfeng 46000000.pfe pfe1: Link is Up - 1Gbps/Full - flow control off&lt;BR /&gt;[ 294.198527] pfeng 46000000.pfe pfe1: Link is Down&lt;BR /&gt;[ 294.198879] pfeng 46000000.pfe pfe2: Link is Down&lt;BR /&gt;[ 294.198897] pfeng 46000000.pfe pfe2: Link is Up - 100Mbps/Full - flow control off&lt;BR /&gt;[ 294.198937] pfeng 46000000.pfe pfe2: Link is Down&lt;BR /&gt;[ 294.199102] pfeng 46000000.pfe: HIF3 not enabled, skipped&lt;BR /&gt;[ 294.199114] pfeng 46000000.pfe: HIF2 stopped&lt;BR /&gt;[ 294.199316] pfeng 46000000.pfe: HIF2 disabled&lt;BR /&gt;[ 294.199326] pfeng 46000000.pfe: HIF1 stopped&lt;BR /&gt;[ 294.199566] pfeng 46000000.pfe: HIF1 disabled&lt;BR /&gt;[ 294.199576] pfeng 46000000.pfe: HIF0 stopped&lt;BR /&gt;[ 294.199841] pfeng 46000000.pfe: HIF0 disabled&lt;BR /&gt;[ 295.173469] pfeng 46000000.pfe: Global poller finished&lt;BR /&gt;[ 295.173550] pfeng 46000000.pfe: Removing default logical interface (pfe0, parent: emac0)&lt;BR /&gt;[ 295.173618] pfeng 46000000.pfe: pfe0 (p0x00000000384bf720) removed from emac0 (p0x00000000f100ce35)&lt;BR /&gt;[ 295.173781] pfeng 46000000.pfe: Removing default logical interface (hif0-logif, parent: hif0)&lt;BR /&gt;[ 295.173839] pfeng 46000000.pfe: hif0-logif (p0x0000000079b9b168) removed from hif0 (p0x0000000009947d5a)&lt;BR /&gt;[ 295.173998] pfeng 46000000.pfe: Removing default logical interface (pfe1, parent: emac1)&lt;BR /&gt;[ 295.174056] pfeng 46000000.pfe: pfe1 (p0x00000000bff17df6) removed from emac1 (p0x00000000b8a05c86)&lt;BR /&gt;[ 295.174211] pfeng 46000000.pfe: Removing default logical interface (hif1-logif, parent: hif1)&lt;BR /&gt;[ 295.174268] pfeng 46000000.pfe: hif1-logif (p0x000000006dd447ee) removed from hif1 (p0x000000007e3d42d0)&lt;BR /&gt;[ 295.174427] pfeng 46000000.pfe: Removing default logical interface (pfe2, parent: emac2)&lt;BR /&gt;[ 295.174485] pfeng 46000000.pfe: pfe2 (p0x0000000068dd0b02) removed from emac2 (p0x00000000158146c3)&lt;BR /&gt;[ 295.174642] pfeng 46000000.pfe: Removing default logical interface (hif2-logif, parent: hif2)&lt;BR /&gt;[ 295.174700] pfeng 46000000.pfe: hif2-logif (p0x00000000ad97132a) removed from hif2 (p0x000000007be1b77a)&lt;BR /&gt;[ 296.029709] pfeng 46000000.pfe: Stopping rtable worker...&lt;BR /&gt;[ 296.029763] pfeng 46000000.pfe: rtable worker stopped&lt;BR /&gt;[ 296.030165] pfeng 46000000.pfe: PFE Platform stopped&lt;BR /&gt;[ 296.061606] s32cc-rtc 40060000.rtc: RTC timer expired before entering in suspend&lt;BR /&gt;[ 296.061617] PM: dpm_run_callback(): platform_pm_suspend+0x0/0x70 returns -5&lt;BR /&gt;[ 296.061642] s32cc-rtc 40060000.rtc: PM: failed to suspend: error -5&lt;BR /&gt;[ 296.061653] PM: Some devices failed to suspend, or early wake event detected&lt;BR /&gt;[ 296.062626] s32cc_fccu 4030c000.fccu: FCCU status is 0 (normal)&lt;BR /&gt;[ 296.081200] phy-s32cc-serdes 40480000.serdes: Using mode 0 for SerDes subsystem&lt;BR /&gt;[ 296.081370] phy-s32cc-serdes 44180000.serdes: Using mode 3 for SerDes subsystem&lt;BR /&gt;[ 296.108669] phy-s32cc-serdes 44180000.serdes: Unstable RX detected on XPCS1&lt;BR /&gt;[ 296.109299] phy-s32cc-serdes 44180000.serdes: Unstable RX detected on XPCS0&lt;BR /&gt;[ 296.109446] pfeng 46000000.pfe: Resuming driver&lt;BR /&gt;[ 296.109494] pfeng 46000000.pfe: PFE port coherency enabled, mask 0x1e&lt;BR /&gt;[ 296.109646] pfeng 46000000.pfe: Interface selected: EMAC0: 0x4 EMAC1: 0x4 EMAC2: 0x7&lt;BR /&gt;[ 296.110331] pfeng 46000000.pfe: PFE controller reset done&lt;BR /&gt;[ 296.110550] pfeng 46000000.pfe: PFE CBUS p0x46000000 mapped @ v0xffffffc011000000 (0x1000000 bytes)&lt;BR /&gt;[ 296.110561] pfeng 46000000.pfe: HW version 0x50300&lt;BR /&gt;[ 296.110569] pfeng 46000000.pfe: Silicon S32G2&lt;BR /&gt;[ 296.111674] pfeng 46000000.pfe: PFE_ERRORS:Parity instance created&lt;BR /&gt;[ 296.111684] pfeng 46000000.pfe: PFE_ERRORS:Watchdog instance created&lt;BR /&gt;[ 296.111694] pfeng 46000000.pfe: BMU1 buffer base: p0xc0000000&lt;BR /&gt;[ 296.111799] pfeng 46000000.pfe: BMU2 buffer base: p0x34000000 (0x80000 bytes)&lt;BR /&gt;[ 296.113083] pfeng 46000000.pfe: register IRQ 71 by name 'PFE BMU IRQ'&lt;BR /&gt;[ 296.113273] pfeng 46000000.pfe: BMU_EMPTY_INT (BMU @ p0x00000000a966d5e7). Pool ready.&lt;BR /&gt;[ 296.113280] pfeng 46000000.pfe: Firmware .elf detected&lt;BR /&gt;[ 296.113288] pfeng 46000000.pfe: BMU_EMPTY_INT (BMU @ p0x000000005a631beb). Pool ready.&lt;BR /&gt;[ 296.113290] pfeng 46000000.pfe: Uploading CLASS firmware&lt;BR /&gt;[ 296.113299] pfeng 46000000.pfe: Selected FW loading OPs to load 8 PEs in parallel&lt;BR /&gt;[ 296.133028] pfeng 46000000.pfe: pfe_ct.h file version"92367c0e25f21f49217a9b08168ad2c8"&lt;BR /&gt;[ 296.149800] pfeng 46000000.pfe: [FW VERSION] 1.6.0, Build: Mar 15 2023, 12:37:54 (), ID: 0x31454650&lt;BR /&gt;[ 296.150171] pfeng 46000000.pfe: EMAC timestamp external mode bitmap: 0&lt;BR /&gt;[ 296.150222] pfeng 46000000.pfe: Uploading UTIL firmware&lt;BR /&gt;[ 296.150227] pfeng 46000000.pfe: Selected FW loading OPs to load 1 PEs in parallel&lt;BR /&gt;[ 296.152699] pfeng 46000000.pfe: pfe_ct.h file version"92367c0e25f21f49217a9b08168ad2c8"&lt;BR /&gt;[ 296.160448] pfeng 46000000.pfe: FW feature: drv_run_on_g3&lt;BR /&gt;[ 296.160456] pfeng 46000000.pfe: FW feature: jumbo_frames&lt;BR /&gt;-sh[ 296.160464] pfeng 46000000.pfe: FW feature: software_vlan_table&lt;BR /&gt;: [ 296.160471] pfeng 46000000.pfe: FW feature: timestamping&lt;BR /&gt;e[ 296.160476] pfeng 46000000.pfe: FW feature: qos_mapping&lt;BR /&gt;c[ 296.160482] pfeng 46000000.pfe: FW feature: core_functionality&lt;BR /&gt;h[ 296.160488] pfeng 46000000.pfe: FW feature: extended_features&lt;BR /&gt;o[ 296.160495] pfeng 46000000.pfe: FW feature: flexible_router&lt;BR /&gt;:[ 296.160500] pfeng 46000000.pfe: FW feature: validate_hif_csum&lt;BR /&gt;[ 296.160507] pfeng 46000000.pfe: FW feature: err051211_workaround&lt;BR /&gt;w[ 296.160513] pfeng 46000000.pfe: FW feature: IPsec&lt;BR /&gt;r[ 296.160519] pfeng 46000000.pfe: FW feature: l2_bridge_aging&lt;BR /&gt;i[ 296.160526] pfeng 46000000.pfe: FW feature: receive_malformed&lt;BR /&gt;t[ 296.160532] pfeng 46000000.pfe: FW feature: ptp_conf_check&lt;BR /&gt;e[ 296.160538] pfeng 46000000.pfe: FW feature: vlan_conf_check&lt;BR /&gt;[ 296.160545] pfeng 46000000.pfe: FW feature: hash_load_spread&lt;BR /&gt;e[ 296.160552] pfeng 46000000.pfe: FW feature: egress_vlan&lt;BR /&gt;r[ 296.160558] pfeng 46000000.pfe: FW feature: ingress_vlan&lt;BR /&gt;r[ 296.160564] pfeng 46000000.pfe: FW feature: safety&lt;BR /&gt;o[ 296.162875] pfeng 46000000.pfe: VLAN ID incorrect or not set. Using default VLAN ID = 0x01.&lt;BR /&gt;r[ 296.162881] pfeng 46000000.pfe: VLAN stats size incorrect or not set. Using default VLAN stats size = 20.&lt;BR /&gt;:[ 296.162976] pfeng 46000000.pfe: Software vlan hash table @ p0x20001208&lt;BR /&gt;[ 296.163162] pfeng 46000000.pfe: Fall-back bridge domain @ 0x20000a44 (class)&lt;BR /&gt;I[ 296.163169] pfeng 46000000.pfe: Default bridge domain @ 0x20000a3c (class)&lt;BR /&gt;n[ 296.163523] pfeng 46000000.pfe: Routing table created, Hash Table @ p0x34080000, Pool @ p0x34088000 (65536 bytes)&lt;BR /&gt;p[ 296.163801] pfeng 46000000.pfe: Feature err051211_workaround: DISABLED&lt;BR /&gt;u[ 296.165477] pfeng 46000000.pfe: HIF0 enabled&lt;BR /&gt;t[ 296.165703] pfeng 46000000.pfe: HIF1 enabled&lt;BR /&gt;/[ 296.165969] pfeng 46000000.pfe: HIF2 enabled&lt;BR /&gt;o[ 296.165975] pfeng 46000000.pfe: HIF3 not configured, skipped&lt;BR /&gt;u[ 296.166014] pfeng 46000000.pfe: TX clocks on EMAC0 restarted&lt;BR /&gt;t[ 296.166042] pfeng 46000000.pfe: RX clocks on EMAC0 restarted&lt;BR /&gt;p[ 296.166052] pfeng 46000000.pfe pfe0: Host LLTX disabled&lt;BR /&gt;u[ 296.166476] pfeng 46000000.pfe pfe0: Enable HIF0&lt;BR /&gt;t[ 296.166644] pfeng 46000000.pfe pfe0: setting MAC addr: 00:01:be:be:ef:11&lt;BR /&gt;[ 296.166688] pfeng 46000000.pfe pfe0: PTP HW addend 0x80000000, max_adj configured to 46566128 ppb&lt;BR /&gt;e[ 296.166699] pfeng 46000000.pfe: IEEE1588: Input Clock: 200000000Hz, Output: 100000000Hz, Accuracy: 10.0ns&lt;BR /&gt;r[ 296.167297] pfeng 46000000.pfe pfe0: Registered PTP HW clock successfully on EMAC0&lt;BR /&gt;r[ 296.167310] pfeng 46000000.pfe: HIF0 started&lt;BR /&gt;o[ 296.167663] pfeng 46000000.pfe pfe0: configuring for fixed/sgmii link mode&lt;BR /&gt;r[ 296.167821] pfeng 46000000.pfe pfe0: Link is Up - 1Gbps/Full - flow control off&lt;BR /&gt;[ 296.167894] pfeng 46000000.pfe: TX clocks on EMAC1 restarted&lt;/P&gt;&lt;P&gt;[ 296.167922] pfeng 46000000.pfe: RX clocks on EMAC1 restarted&lt;BR /&gt;[ 296.167930] pfeng 46000000.pfe pfe1: Host LLTX disabled&lt;BR /&gt;[ 296.168345] pfeng 46000000.pfe pfe1: Enable HIF1&lt;BR /&gt;[ 296.168513] pfeng 46000000.pfe pfe1: setting MAC addr: 00:01:be:be:ef:22&lt;BR /&gt;[ 296.168547] pfeng 46000000.pfe pfe1: PTP HW addend 0x80000000, max_adj configured to 46566128 ppb&lt;BR /&gt;[ 296.168556] pfeng 46000000.pfe: IEEE1588: Input Clock: 200000000Hz, Output: 100000000Hz, Accuracy: 10.0ns&lt;BR /&gt;[ 296.169034] pfeng 46000000.pfe pfe1: Registered PTP HW clock successfully on EMAC1&lt;BR /&gt;[ 296.169045] pfeng 46000000.pfe: HIF1 started&lt;BR /&gt;[ 296.169388] pfeng 46000000.pfe pfe1: configuring for fixed/sgmii link mode&lt;BR /&gt;r[ 296.169517] pfeng 46000000.pfe pfe1: Link is Up - 1Gbps/Full - flow control off&lt;BR /&gt;o[ 296.169554] pfeng 46000000.pfe pfe2: Host LLTX disabled&lt;BR /&gt;o[ 296.169961] pfeng 46000000.pfe pfe2: Enable HIF2&lt;BR /&gt;t[ 296.170128] pfeng 46000000.pfe pfe2: setting MAC addr: 00:01:be:be:ef:33&lt;BR /&gt;@[ 296.170151] pfeng 46000000.pfe pfe2: PTP HW addend 0x80000000, max_adj configured to 46566128 ppb&lt;BR /&gt;s[ 296.170162] pfeng 46000000.pfe: IEEE1588: Input Clock: 200000000Hz, Output: 100000000Hz, Accuracy: 10.0ns&lt;BR /&gt;3[ 296.170611] pfeng 46000000.pfe pfe2: Registered PTP HW clock successfully on EMAC2&lt;BR /&gt;2[ 296.170621] pfeng 46000000.pfe: HIF2 started&lt;BR /&gt;g[ 296.170964] pfeng 46000000.pfe pfe2: configuring for fixed/rmii link mode&lt;BR /&gt;2[ 296.170995] pfeng 46000000.pfe pfe2: Link is Up - 100Mbps/Full - flow control off&lt;BR /&gt;7[ 296.278873] OOM killer enabled.&lt;BR /&gt;4[ 296.278882] Restarting tasks ... done.&lt;BR /&gt;a[ 296.289699] PM: suspend exit&lt;/P&gt;&lt;P&gt;```&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Any idea why I can't go to sleep?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;--Jordan&lt;/P&gt;&lt;/DIV&gt;</description>
      <pubDate>Tue, 19 Mar 2024 15:50:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Wakeup-on-CAN-CAN-FD-App-Note/m-p/1831282#M6322</guid>
      <dc:creator>jmelnych_ford</dc:creator>
      <dc:date>2024-03-19T15:50:48Z</dc:date>
    </item>
    <item>
      <title>Re: Wakeup on CAN/CAN-FD App Note</title>
      <link>https://community.nxp.com/t5/S32G/Wakeup-on-CAN-CAN-FD-App-Note/m-p/1831318#M6323</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;Can you confirm which BSP version are you using? Are you using any NXP reference board? Also, did you replicate successfully the example shown under the BSP User Manual?&lt;/P&gt;
&lt;P&gt;If the platform is waking up, it should be that the wake-up routine was triggered, hence it wakes up.&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
      <pubDate>Tue, 19 Mar 2024 16:50:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Wakeup-on-CAN-CAN-FD-App-Note/m-p/1831318#M6323</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2024-03-19T16:50:35Z</dc:date>
    </item>
    <item>
      <title>Re: Wakeup on CAN/CAN-FD App Note</title>
      <link>https://community.nxp.com/t5/S32G/Wakeup-on-CAN-CAN-FD-App-Note/m-p/1831329#M6324</link>
      <description>BSP 36. This is on a custom board so I can't use the same pin in the example. I did check that the pins are wkpu compatible in the io-mux spreadsheet</description>
      <pubDate>Tue, 19 Mar 2024 17:20:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Wakeup-on-CAN-CAN-FD-App-Note/m-p/1831329#M6324</guid>
      <dc:creator>jmelnych_ford</dc:creator>
      <dc:date>2024-03-19T17:20:14Z</dc:date>
    </item>
    <item>
      <title>Re: Wakeup on CAN/CAN-FD App Note</title>
      <link>https://community.nxp.com/t5/S32G/Wakeup-on-CAN-CAN-FD-App-Note/m-p/1831455#M6325</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;Thanks for your feedback. Can you confirm that your I/O's are not being turned down? Do you have any pull-ups on the signals?&lt;/P&gt;
&lt;P&gt;You could change the IRQ type to RISING, and apply voltage to the signal.&lt;/P&gt;
&lt;P&gt;But still, we can recommend replicating as close as possible the example shown under the BSP User Manual, then continue applying modifications.&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
      <pubDate>Tue, 19 Mar 2024 21:24:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Wakeup-on-CAN-CAN-FD-App-Note/m-p/1831455#M6325</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2024-03-19T21:24:36Z</dc:date>
    </item>
    <item>
      <title>Re: Wakeup on CAN/CAN-FD App Note</title>
      <link>https://community.nxp.com/t5/S32G/Wakeup-on-CAN-CAN-FD-App-Note/m-p/1832279#M6340</link>
      <description>&lt;P&gt;Hey Daniel,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I tracked it down to a yocto issue.&amp;nbsp; Looks like the patches weren't getting applied.....&amp;nbsp; I'm now able to wakeup on falling edge as expected.&amp;nbsp; However when I wake back up I get these errors:&lt;/P&gt;&lt;P&gt;```&lt;/P&gt;&lt;P&gt;[ 611.391812] Restarting tasks ... done.&lt;BR /&gt;[ 611.409130] PM: suspend exit&lt;BR /&gt;[ 612.389538] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 613.413533] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 614.437538] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 615.461534] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 616.485530] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 617.509535] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 618.533527] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 618.533544] pfeng 46000000.pfe: HM event storage is full, no further events will be stored.&lt;BR /&gt;[ 619.557528] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 620.581529] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 621.605530] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 622.629529] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 623.653529] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 624.677530] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 625.701528] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 626.725528] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 627.749525] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 628.773528] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 629.797529] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 630.821529] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 631.845528] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 632.869528] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 633.893528] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 634.917529] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 635.941572] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 636.965493] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 637.993492] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 639.013526] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 640.037547] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 641.061491] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 642.085526] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 643.109493] pfeng 46000000.pfe: ERR: (PFENG_DEV) event 15 - EMAC2 GPI Watchdog trigered: [pfe_wdt_csr.c:126]&lt;BR /&gt;[ 643.109518] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 644.133493] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;BR /&gt;[ 645.157491] pfeng 46000000.pfe: ERR: (EMAC0) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1635]&lt;/P&gt;&lt;P&gt;```&lt;/P&gt;</description>
      <pubDate>Wed, 20 Mar 2024 19:42:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Wakeup-on-CAN-CAN-FD-App-Note/m-p/1832279#M6340</guid>
      <dc:creator>jmelnych_ford</dc:creator>
      <dc:date>2024-03-20T19:42:49Z</dc:date>
    </item>
    <item>
      <title>Re: Wakeup on CAN/CAN-FD App Note</title>
      <link>https://community.nxp.com/t5/S32G/Wakeup-on-CAN-CAN-FD-App-Note/m-p/1833195#M6355</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;Thanks for your feedback. On regards of those messages, we see the following information was provided:&lt;/P&gt;
&lt;P&gt;"&lt;SPAN&gt;The root cause of this issue is that&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;&lt;SPAN class="ui-provider a b c d e f g h i j k l m n o p q r s t u v w x y z ab ac ae af ag ah ai aj ak"&gt;TF-A clocking framework is not able to inherit state after MCAL previously running on M7 when M7 perform a functional rest.&amp;nbsp;The destructive reset put HW into defined state, so there is no issue.&lt;/SPAN&gt;&lt;/SPAN&gt;"&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
      <pubDate>Thu, 21 Mar 2024 20:33:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Wakeup-on-CAN-CAN-FD-App-Note/m-p/1833195#M6355</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2024-03-21T20:33:10Z</dc:date>
    </item>
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