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    <title>topic Re: S32G274A SGMII Interface in S32G</title>
    <link>https://community.nxp.com/t5/S32G/S32G274A-SGMII-Interface/m-p/1809480#M5934</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;Thanks for your feedback.&lt;/P&gt;
&lt;P&gt;On regards of the following comment:&lt;/P&gt;
&lt;P&gt;"&lt;SPAN&gt;Can you suggest the Linux driver which is specific for BCM89885 phy (Linux version used is 5.10.41).&lt;/SPAN&gt;"&lt;/P&gt;
&lt;P&gt;Under this specific channel, we understand that NXP does not provide any drivers from a different company (in this case, we understand it is a Broadcom PHY). We can recommend contacting your PHY supplier for them to provide further comments on this. We do apologize.&lt;/P&gt;
&lt;P&gt;As for the overall description, we understand that the S32G interfaces "correctly" with the respective PHY. We also understand that the problem is related to the PHY itself, not the MAC, for which we can again recommend contacting your PHY supplier. We do apologize.&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
    <pubDate>Thu, 15 Feb 2024 21:13:52 GMT</pubDate>
    <dc:creator>Daniel-Aguirre</dc:creator>
    <dc:date>2024-02-15T21:13:52Z</dc:date>
    <item>
      <title>S32G274A SGMII Interface</title>
      <link>https://community.nxp.com/t5/S32G/S32G274A-SGMII-Interface/m-p/1809108#M5930</link>
      <description>&lt;P&gt;One of custom board design we are using S32G274A processor, a 1000BASE-T1 PHY interfacing over the SGMII interface details,&lt;/P&gt;&lt;P&gt;Broadcom Part No :&amp;nbsp;BCM89885MA0BWMLG (&lt;/P&gt;&lt;P&gt;The Broadcom PHY chip auto-negation is enabled, configured in Advertise 1000BASE-T1 and 100BASE-T1 secondary.&lt;/P&gt;&lt;P&gt;As of now, processor able to detect the PHY but ping is not coming.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Please let us reasons for ping is not coming.&lt;/P&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Gopala&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 15 Feb 2024 12:45:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G274A-SGMII-Interface/m-p/1809108#M5930</guid>
      <dc:creator>gopalakrishna</dc:creator>
      <dc:date>2024-02-15T12:45:45Z</dc:date>
    </item>
    <item>
      <title>Re: S32G274A SGMII Interface</title>
      <link>https://community.nxp.com/t5/S32G/S32G274A-SGMII-Interface/m-p/1809215#M5931</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;Which BSP version are you using? Which interface are you using?&lt;/P&gt;
&lt;P&gt;Can you share a full boot log about the behavior you are seeing? Under the log, help us adding the&amp;nbsp;&lt;EM&gt;hwconfig&lt;/EM&gt; you have configured.&lt;/P&gt;
&lt;P&gt;Since this is a custom board, we can recommend either opening a ticket or contacting your local NXP representative/FAE/DFAE, given that we are unable to reproduce the specific behavior you are seeing. We do apologize.&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
      <pubDate>Thu, 15 Feb 2024 15:42:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G274A-SGMII-Interface/m-p/1809215#M5931</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2024-02-15T15:42:19Z</dc:date>
    </item>
    <item>
      <title>Re: S32G274A SGMII Interface</title>
      <link>https://community.nxp.com/t5/S32G/S32G274A-SGMII-Interface/m-p/1809296#M5933</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;Currently we are able to read and write all the registers from SGMII and 1000/100Base-T1 register and able to load the Phy driver that support Clause 45.&lt;/P&gt;&lt;P&gt;The issue that we are facing currently is that the PHY is not able to detect the link up status on plugging in of the ethernet cable.&lt;/P&gt;&lt;P&gt;Currently we are using the Generic Linux phy driver as mentioned below&lt;/P&gt;&lt;P&gt;&lt;A href="https://elixir.bootlin.com/linux/latest/source/drivers/net/phy/phy-c45.c" target="_blank"&gt;https://elixir.bootlin.com/linux/latest/source/drivers/net/phy/phy-c45.c&lt;/A&gt;&lt;/P&gt;&lt;P&gt;Can you suggest the Linux driver which is specific for BCM89885 phy (Linux version used is 5.10.41).&lt;/P&gt;&lt;P&gt;PHY Interface to Processor:&lt;/P&gt;&lt;P&gt;SERDES1_LANE1 (PFE1)&lt;/P&gt;&lt;P&gt;SERDES1_LANE0 (PFE0)&lt;/P&gt;&lt;P&gt;These are interfaces we are using.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Based on Clause 45 and we are able to read the SGMII Register set after doing the register write as shown in attached image also attached the register value that we could able to read from PHY(SGMII_reg_read.txt).&lt;/P&gt;</description>
      <pubDate>Thu, 15 Feb 2024 17:28:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G274A-SGMII-Interface/m-p/1809296#M5933</guid>
      <dc:creator>gopalakrishna</dc:creator>
      <dc:date>2024-02-15T17:28:55Z</dc:date>
    </item>
    <item>
      <title>Re: S32G274A SGMII Interface</title>
      <link>https://community.nxp.com/t5/S32G/S32G274A-SGMII-Interface/m-p/1809480#M5934</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;Thanks for your feedback.&lt;/P&gt;
&lt;P&gt;On regards of the following comment:&lt;/P&gt;
&lt;P&gt;"&lt;SPAN&gt;Can you suggest the Linux driver which is specific for BCM89885 phy (Linux version used is 5.10.41).&lt;/SPAN&gt;"&lt;/P&gt;
&lt;P&gt;Under this specific channel, we understand that NXP does not provide any drivers from a different company (in this case, we understand it is a Broadcom PHY). We can recommend contacting your PHY supplier for them to provide further comments on this. We do apologize.&lt;/P&gt;
&lt;P&gt;As for the overall description, we understand that the S32G interfaces "correctly" with the respective PHY. We also understand that the problem is related to the PHY itself, not the MAC, for which we can again recommend contacting your PHY supplier. We do apologize.&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
      <pubDate>Thu, 15 Feb 2024 21:13:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G274A-SGMII-Interface/m-p/1809480#M5934</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2024-02-15T21:13:52Z</dc:date>
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