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    <title>topic Re: S32G A core reads and writes SRAM in S32G</title>
    <link>https://community.nxp.com/t5/S32G/S32G-A-core-reads-and-writes-SRAM/m-p/1796355#M5795</link>
    <description>&lt;P&gt;mw.b mw.w mw.l cannot be cleared ???, mw.q and cp can be cleared&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="learnx_1-1706353021629.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/260380iF0344466AB76BD2E/image-size/medium?v=v2&amp;amp;px=400" role="button" title="learnx_1-1706353021629.png" alt="learnx_1-1706353021629.png" /&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="learnx_2-1706353030082.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/260381iAA464C6829954772/image-size/medium?v=v2&amp;amp;px=400" role="button" title="learnx_2-1706353030082.png" alt="learnx_2-1706353030082.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Sat, 27 Jan 2024 10:57:26 GMT</pubDate>
    <dc:creator>learnx</dc:creator>
    <dc:date>2024-01-27T10:57:26Z</dc:date>
    <item>
      <title>S32G A core reads and writes SRAM</title>
      <link>https://community.nxp.com/t5/S32G/S32G-A-core-reads-and-writes-SRAM/m-p/1796332#M5792</link>
      <description>&lt;P&gt;Hardware version: S32G274A EVB&lt;BR /&gt;Software BSP version: BSP33.0&lt;BR /&gt;Software firmware (use official image):&lt;BR /&gt;1. binaries_bsp33.0/s32g274ardb2/fsl-image-auto-s32g274ardb2.sdcard 2. binaries_bsp33.0/s32g274ardb2/fip.s32-sdcard&lt;BR /&gt;Debugger: Lauterbach&lt;BR /&gt;Startup method: SD card startup&lt;/P&gt;&lt;P&gt;Question: Start the A core from the SD card, stay in uboot, use Lauterbach to attach the A core, check the 0x34000000 memory, and display ????. Another phenomenon is that when using the command md.b 0x34000000 0x1000 under uboot, it will crash and then automatically reset.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="learnx_0-1706327401780.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/260372iDE19E438C0D2477F/image-size/medium?v=v2&amp;amp;px=400" role="button" title="learnx_0-1706327401780.png" alt="learnx_0-1706327401780.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sat, 27 Jan 2024 03:50:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G-A-core-reads-and-writes-SRAM/m-p/1796332#M5792</guid>
      <dc:creator>learnx</dc:creator>
      <dc:date>2024-01-27T03:50:19Z</dc:date>
    </item>
    <item>
      <title>Re: S32G A core reads and writes SRAM</title>
      <link>https://community.nxp.com/t5/S32G/S32G-A-core-reads-and-writes-SRAM/m-p/1796355#M5795</link>
      <description>&lt;P&gt;mw.b mw.w mw.l cannot be cleared ???, mw.q and cp can be cleared&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="learnx_1-1706353021629.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/260380iF0344466AB76BD2E/image-size/medium?v=v2&amp;amp;px=400" role="button" title="learnx_1-1706353021629.png" alt="learnx_1-1706353021629.png" /&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="learnx_2-1706353030082.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/260381iAA464C6829954772/image-size/medium?v=v2&amp;amp;px=400" role="button" title="learnx_2-1706353030082.png" alt="learnx_2-1706353030082.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sat, 27 Jan 2024 10:57:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G-A-core-reads-and-writes-SRAM/m-p/1796355#M5795</guid>
      <dc:creator>learnx</dc:creator>
      <dc:date>2024-01-27T10:57:26Z</dc:date>
    </item>
    <item>
      <title>Re: S32G A core reads and writes SRAM</title>
      <link>https://community.nxp.com/t5/S32G/S32G-A-core-reads-and-writes-SRAM/m-p/1796451#M5797</link>
      <description>&lt;P&gt;Can anyone help answer this question?&lt;/P&gt;</description>
      <pubDate>Mon, 29 Jan 2024 01:29:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G-A-core-reads-and-writes-SRAM/m-p/1796451#M5797</guid>
      <dc:creator>learnx</dc:creator>
      <dc:date>2024-01-29T01:29:40Z</dc:date>
    </item>
    <item>
      <title>Re: S32G A core reads and writes SRAM</title>
      <link>https://community.nxp.com/t5/S32G/S32G-A-core-reads-and-writes-SRAM/m-p/1797063#M5802</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;We understand that you are using an EVB platform but see that you are using an RDB2 image, can you confirm that the behavior remains the same by using the EVB related image?&lt;/P&gt;
&lt;P&gt;Also, on regards of the "&lt;SPAN&gt;when using the command md.b 0x34000000 0x1000 under uboot, it will crash and then automatically reset.&lt;/SPAN&gt;" comment, this seems to be related to the memory not being initialized, we can run the command after writing to the related address:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DanielAguirre_0-1706551190916.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/260604iB469E0FF99E52F5B/image-size/medium?v=v2&amp;amp;px=400" role="button" title="DanielAguirre_0-1706551190916.png" alt="DanielAguirre_0-1706551190916.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;As for the second behavior you are showing, we are unable to reproduce your outcome due to the lack of tools from our side. Still, we see the following from our side:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DanielAguirre_1-1706551458137.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/260605iAF247C8F02582CAC/image-size/medium?v=v2&amp;amp;px=400" role="button" title="DanielAguirre_1-1706551458137.png" alt="DanielAguirre_1-1706551458137.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;Don't know if this information helps.&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
      <pubDate>Mon, 29 Jan 2024 18:05:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G-A-core-reads-and-writes-SRAM/m-p/1797063#M5802</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2024-01-29T18:05:25Z</dc:date>
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