topic Re: s32g3 pcie issues in S32G

s32g3 pcie issues

zhangmeng6 — Mon, 15 Jan 2024 02:52:07 GMT

Hi, nxp:

I am learning pcie.Now I have a problem.

The hardware connection is J5(another company's chip) directly connected to s32g3,J5 is RC，s32g3 is ep.

I can now read the DID and VID of ep on RC side as follows. But starting at 0xc reads out as 0xff.

What's the reason?

root@j5dvb:~# lspci -x
00:00.0 Class 0604: Device 16c3:abcd (rev 01)
00: c3 16 cd ab 07 05 11 40 01 00 04 06 00 00 01 00
10: 00 00 10 60 00 00 00 00 00 01 ff 00 f0 00 00 20
20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 02 01 02 00

01:00.0 Class 0b80: Device 1957:4300 (rev 01)
00: 57 19 00 43 03 00 10 00 01 00 80 0b ff ff ff ff
10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff

Re: s32g3 pcie issues

zhangmeng6 — Tue, 23 Jan 2024 05:51:39 GMT

Hi, nxp:

Is there anything update? It seems to have something to do with the reset timing of the serdes,If I add a delay of 100ms after deassert_reset(serdes) during the initialization of serdes.I can read the ep config on the RC side.

I read the RMS32SERDES documentation，Only one description of PCIE_PHY_MPLLA_CTRL[MPLL_STATE] was found, but this seems to be irrelevant. I continued to initialize the register after asserting that its BIT30 was 1, and the problem remained.

--- a/kernel/drivers/phy/freescale/phy-fsl-s32gen1-serdes.c
+++ b/kernel/drivers/phy/freescale/phy-fsl-s32gen1-serdes.c
@@ -865,6 +865,8 @@ static int init_serdes(struct serdes *serdes)
if (ret)
return ret;

+ mdelay(100);
+
dev_info(serdes->dev, "Using mode %d for SerDes subsystem\n",
ctrl->ss_mode);