S32GのトピックRe: S32G2 set PCIe0 to single lane

S32G2 set PCIe0 to single lane

lodo1234 — Wed, 22 Nov 2023 20:46:21 GMT

I'm trying to set the S32G2 PCIe0 to a single lane in u-boot with the following hwconfig:

hwconfig=serdes0:mode=pcie,clock=ext;pcie0:mode=rc&sgmii,clock=ext,fmhz=100,xpcs_mode=1

However, this does not seem to take effect based on the following startup output and output from lspci

[ 2.388693] phy-s32cc-serdes 40480000.serdes: Using mode 0 for SerDes subsystem

Port #0, Speed 8GT/s, Width x2, ASPM L1, Exit Latency L1 <16us

I've also tried changing the num-lanes in the dts file, but my understanding from the BSP manual that this does not have an effect.

I am using BSP36

Re: S32G2 set PCIe0 to single lane

Daniel-Aguirre — Thu, 23 Nov 2023 17:51:31 GMT

Hi,

We understand that SerDes 0 Mode 1 was not supported under the BSP's due to a bug under the GMAC SGMII interface. It seems that a solution has been provided for this situation, but we will confirm if it is correctly implemented and in which version was implemented (if any at this moment).

Please, let us know.

Re: S32G2 set PCIe0 to single lane

lodo1234 — Mon, 27 Nov 2023 18:58:40 GMT

Thanks for your response. To be clear, are you looking for me to do something at this point? My interpretation is you are going confirm if the bug fix has been correctly implemented and in which version of the BSP.

Re: S32G2 set PCIe0 to single lane

Daniel-Aguirre — Mon, 27 Nov 2023 22:05:21 GMT

Hi,

Thanks for your feedback. There was no action point from your side that we were expecting. We apologize if it seemed that way.

We have received the following update from our side:

If customer wants to use 1 lane for PCIE, please try the following hwconfig (mode2)

setenv hwconﬁg "serdes0:mode=pcie&xpcs1,clock=ext,fmhz=100;pcie0:mode=rc;xpcs0_1:speed=1G"

Please, let us know.