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    <title>S32G中的主题 DSPI interface issu while sending union buffer</title>
    <link>https://community.nxp.com/t5/S32G/DSPI-interface-issu-while-sending-union-buffer/m-p/1302589#M49</link>
    <description>&lt;P&gt;Hi All,&lt;/P&gt;&lt;P&gt;I am using a code example from the Power PC library to develop my DSPI application.&lt;/P&gt;&lt;P&gt;I have an issue with the data transferred on the SPI bus.&lt;/P&gt;&lt;P&gt;I ma using a SPI inspector to visualize the the data sent on the SPI bus. I remark that I am only sending the first value of the buffer (master_send[0]) even if I loop trough the whole buffer?&lt;/P&gt;&lt;P&gt;for (count1 = 0; count1 &amp;lt; 2; count1++)&lt;BR /&gt;{&lt;BR /&gt;Pointer = (uint16_t *)&amp;amp;master_send[count1].XS_Spd_In_Data[0];&lt;BR /&gt;Dspi_status = DSPI_MasterTransfer(INST_DSPI1, Pointer, &amp;amp;master_receive[0], NUMBER_OF_FRAMES);&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;Do you have any idea about the source of this problem? Thank you in advance.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Capture d’écran 2021-07-05 222610.png" style="width: 921px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/148825iA768CED517733A8F/image-size/large?v=v2&amp;amp;px=999" role="button" title="Capture d’écran 2021-07-05 222610.png" alt="Capture d’écran 2021-07-05 222610.png" /&gt;&lt;/span&gt;&amp;nbsp;&lt;/P&gt;&lt;BLOCKQUOTE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;/*&lt;BR /&gt;* Copyright 2017 NXP&lt;BR /&gt;* All rights reserved.&lt;BR /&gt;*&lt;BR /&gt;* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR&lt;BR /&gt;* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES&lt;BR /&gt;* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.&lt;BR /&gt;* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,&lt;BR /&gt;* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES&lt;BR /&gt;* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR&lt;BR /&gt;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)&lt;BR /&gt;* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,&lt;BR /&gt;* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING&lt;BR /&gt;* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF&lt;BR /&gt;* THE POSSIBILITY OF SUCH DAMAGE.&lt;BR /&gt;*/&lt;BR /&gt;/* ###################################################################&lt;BR /&gt;** Filename : main.c&lt;BR /&gt;** Project : pit_periodic_interrupt_mpc5748g&lt;BR /&gt;** Processor : MPC5748G_324&lt;BR /&gt;** Version : Driver 01.00&lt;BR /&gt;** Compiler : GNU C Compiler&lt;BR /&gt;** Date/Time : 2017-03-15, 12:21, # CodeGen: 6&lt;BR /&gt;** Abstract :&lt;BR /&gt;** Main module.&lt;BR /&gt;** This module contains user's application code.&lt;BR /&gt;** Settings :&lt;BR /&gt;** Contents :&lt;BR /&gt;** No public methods&lt;BR /&gt;**&lt;BR /&gt;** ###################################################################*/&lt;BR /&gt;/*!&lt;BR /&gt;** @file main.c&lt;BR /&gt;** @version 01.00&lt;BR /&gt;** @brief&lt;BR /&gt;** Main module.&lt;BR /&gt;** This module contains user's application code.&lt;BR /&gt;*/&lt;BR /&gt;/*!&lt;BR /&gt;** @addtogroup main_module main module documentation&lt;BR /&gt;** @{&lt;BR /&gt;*/&lt;BR /&gt;/* MODULE main */&lt;BR /&gt;/* Including needed modules to compile this module/procedure */&lt;BR /&gt;#include "Cpu.h"&lt;BR /&gt;#include "pit1.h"&lt;BR /&gt;#include "clockMan1.h"&lt;BR /&gt;#include "pin_mux.h"&lt;BR /&gt;#include "dspi1.h"&lt;BR /&gt;#include "MC20XS4200_Drv.h"&lt;BR /&gt;volatile int exit_code = 0;&lt;/P&gt;&lt;P&gt;typedef union&lt;BR /&gt;{&lt;BR /&gt;uint16_t XS_Spd_In_Data[7];&lt;BR /&gt;struct&lt;BR /&gt;{&lt;BR /&gt;TstIO_eSPD_STATR_In_Bits XS_StartIn; //Start register&lt;BR /&gt;TstIO_eSPD_PWMR_In_Bits XS_PwmIn; //pwm register&lt;BR /&gt;TstIO_eSPD_CONFR_In_Bits XS_ConfIn; //configuration register&lt;BR /&gt;TstIO_eSPD_OCR_In_Bits XS_OcrIn; //ocr register&lt;BR /&gt;TstIO_eSPD_RETRYR_In_Bits XS_RetrayIn;//Retry register&lt;BR /&gt;TstIO_eSPD_GCR_In_Bits XS_GcrIn; //GCR register&lt;BR /&gt;uint16_t XS_CalbIn; //Calibration register&lt;BR /&gt;};&lt;BR /&gt;} XS_SpdInRegsData;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;#define BUFFER_SIZE 7U&lt;BR /&gt;#define NUMBER_OF_FRAMES 7U&lt;BR /&gt;#define TIMEOUT 1000U&lt;BR /&gt;/* User includes (#include below this line is not maintained by Processor Expert) */&lt;BR /&gt;/* This example is setup to work by default with DEVKIT. To use it with other boards&lt;BR /&gt;please comment the following line&lt;BR /&gt;*/&lt;/P&gt;&lt;P&gt;/* Write your local variable definition here */&lt;/P&gt;&lt;P&gt;XS_SpdInRegsData master_send[2]={0};&lt;BR /&gt;uint16_t master_send_cache[7 * 2];&lt;BR /&gt;status_t Dspi_status;&lt;BR /&gt;dspi_transfer_status_t DSp_Busy;&lt;BR /&gt;//uint8_t master_receive[BUFFER_SIZE];&lt;BR /&gt;uint16_t count;&lt;BR /&gt;uint8_t master_receive[BUFFER_SIZE];&lt;BR /&gt;uint8_t slave_send[] = { 1, 2, 3, 4, 5, 6, 7 };&lt;BR /&gt;uint8_t slave_receive[BUFFER_SIZE];&lt;BR /&gt;uint16_t count1 = 0;&lt;BR /&gt;uint16_t count2;&lt;BR /&gt;static uint16_t DutyCycle = 0;&lt;BR /&gt;uint16_t *Pointer = NULL;&lt;BR /&gt;#define DEVKIT&lt;BR /&gt;#ifdef DEVKIT&lt;BR /&gt;#define PORT PTA&lt;BR /&gt;#define LED 10 /* pin PA[10] - LED3 (DS4) on DEV-KIT */&lt;BR /&gt;#else&lt;BR /&gt;#define PORT PTG&lt;BR /&gt;#define LED 2 /* pin PG[2] - LED1 (DS2) on Motherboard */&lt;BR /&gt;#endif&lt;BR /&gt;void PIT_Ch0_IRQHandler(void)&lt;BR /&gt;{&lt;BR /&gt;PINS_DRV_TogglePins(PORT, (1 &amp;lt;&amp;lt; LED));&lt;BR /&gt;PIT_DRV_ClearStatusFlags(INST_PIT1, pit1_ChnConfig0.hwChannel); /* Clear channel 0 interrupt flag */&lt;/P&gt;&lt;P&gt;/* update the the period */&lt;BR /&gt;(void) des_MC20XS4200_PwmUpdate(&amp;amp;master_send[0], DutyCycle);&lt;/P&gt;&lt;P&gt;for (count1 = 0; count1 &amp;lt; 2; count1++)&lt;BR /&gt;{&lt;BR /&gt;Pointer = (uint16_t *)&amp;amp;master_send[count1].XS_Spd_In_Data[0];&lt;BR /&gt;Dspi_status = DSPI_MasterTransfer(INST_DSPI1, Pointer, &amp;amp;master_receive[0], NUMBER_OF_FRAMES);&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;}&lt;BR /&gt;/*!&lt;BR /&gt;\brief The main function for the project.&lt;BR /&gt;\details The startup initialization sequence is the following:&lt;BR /&gt;* - startup asm routine&lt;BR /&gt;* - main()&lt;BR /&gt;*/&lt;BR /&gt;int main(void)&lt;BR /&gt;{&lt;BR /&gt;/*** Processor Expert internal initialization. DON'T REMOVE THIS CODE!!! ***/&lt;BR /&gt;#ifdef PEX_RTOS_INIT&lt;BR /&gt;PEX_RTOS_INIT(); /* Initialization of the selected RTOS. Macro is defined by the RTOS component. */&lt;BR /&gt;#endif&lt;BR /&gt;/*** End of Processor Expert internal initialization. ***/&lt;BR /&gt;/* Initialize clock gate*/&lt;BR /&gt;CLOCK_SYS_Init(g_clockManConfigsArr, CLOCK_MANAGER_CONFIG_CNT,&lt;BR /&gt;g_clockManCallbacksArr, CLOCK_MANAGER_CALLBACK_CNT);&lt;BR /&gt;CLOCK_SYS_UpdateConfiguration(0U, CLOCK_MANAGER_POLICY_AGREEMENT);&lt;/P&gt;&lt;P&gt;/* Initialize and configure pins */&lt;BR /&gt;PINS_DRV_Init(NUM_OF_CONFIGURED_PINS, g_pin_mux_InitConfigArr);&lt;/P&gt;&lt;P&gt;/*&lt;BR /&gt;*&lt;BR /&gt;* Init the DSPI peripheral*/&lt;BR /&gt;/* SPI master configuration: clock speed: 500 kHz, 8 bits/frame, MSB first */&lt;BR /&gt;DSPI_MasterInit(DSPI0_INSTANCE, &amp;amp;dspi1State, &amp;amp;dspi1_MasterInitConfig0);&lt;/P&gt;&lt;P&gt;/* Configure delay between transfer, delay between SCK and PCS and delay between PCS and SCK */&lt;BR /&gt;DSPI_MasterSetDelay(DSPI0_INSTANCE, 1, 1, 1);&lt;/P&gt;&lt;P&gt;/*&lt;BR /&gt;*&lt;BR /&gt;* Init the PIT peripheral*/&lt;BR /&gt;/* Initialize PIT */&lt;BR /&gt;PIT_DRV_Init(INST_PIT1, &amp;amp;pit1_InitConfig);&lt;/P&gt;&lt;P&gt;/* Initialize channel 0 */&lt;BR /&gt;PIT_DRV_InitChannel(INST_PIT1, &amp;amp;pit1_ChnConfig0);&lt;/P&gt;&lt;P&gt;/* Start channel 0 counting */&lt;BR /&gt;PIT_DRV_StartChannel(INST_PIT1, pit1_ChnConfig0.hwChannel);&lt;/P&gt;&lt;P&gt;/* Init */&lt;BR /&gt;DutyCycle = 0;&lt;BR /&gt;/*&lt;BR /&gt;*&lt;BR /&gt;* Init the uart peripheral*/&lt;/P&gt;&lt;P&gt;/* Initialize the master send buffer */&lt;BR /&gt;(void) des_MC20XS4200_Config(&amp;amp;master_send[0]);&lt;/P&gt;&lt;P&gt;/* Send CAFE to test SPI communication */&lt;BR /&gt;for (count1 = 0; count1 &amp;lt; 2; count1++)&lt;BR /&gt;{&lt;BR /&gt;Pointer = (uint16_t *)&amp;amp;master_send[count1].XS_Spd_In_Data[0];&lt;BR /&gt;Dspi_status = DSPI_MasterTransfer(INST_DSPI1,Pointer, &amp;amp;master_receive[0],NUMBER_OF_FRAMES);&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;}&lt;/P&gt;&lt;P&gt;/*** Don't write any code pass this line, or it will be deleted during code generation. ***/&lt;BR /&gt;/*** RTOS startup code. Macro PEX_RTOS_START is defined by the RTOS component. DON'T MODIFY THIS CODE!!! ***/&lt;BR /&gt;#ifdef PEX_RTOS_START&lt;BR /&gt;PEX_RTOS_START(); /* Startup of the selected RTOS. Macro is defined by the RTOS component. */&lt;BR /&gt;#endif&lt;BR /&gt;/*** End of RTOS startup code. ***/&lt;BR /&gt;/*** Processor Expert end of main routine. DON'T MODIFY THIS CODE!!! ***/&lt;BR /&gt;for(;;) {&lt;BR /&gt;if(exit_code != 0) {&lt;BR /&gt;break;&lt;BR /&gt;}&lt;BR /&gt;}&lt;BR /&gt;return exit_code;&lt;BR /&gt;/*** Processor Expert end of main routine. DON'T WRITE CODE BELOW!!! ***/&lt;BR /&gt;} /*** End of main routine. DO NOT MODIFY THIS TEXT!!! ***/&lt;BR /&gt;/* END main */&lt;BR /&gt;/*!&lt;BR /&gt;** @}&lt;BR /&gt;*/&lt;BR /&gt;/*&lt;BR /&gt;** ###################################################################&lt;BR /&gt;**&lt;BR /&gt;** This file was created by Processor Expert 10.1 [05.21]&lt;BR /&gt;** for the NXP C55 series of microcontrollers.&lt;BR /&gt;**&lt;BR /&gt;** ###################################################################&lt;BR /&gt;*/&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Mon, 05 Jul 2021 20:32:52 GMT</pubDate>
    <dc:creator>InHome</dc:creator>
    <dc:date>2021-07-05T20:32:52Z</dc:date>
    <item>
      <title>DSPI interface issu while sending union buffer</title>
      <link>https://community.nxp.com/t5/S32G/DSPI-interface-issu-while-sending-union-buffer/m-p/1302589#M49</link>
      <description>&lt;P&gt;Hi All,&lt;/P&gt;&lt;P&gt;I am using a code example from the Power PC library to develop my DSPI application.&lt;/P&gt;&lt;P&gt;I have an issue with the data transferred on the SPI bus.&lt;/P&gt;&lt;P&gt;I ma using a SPI inspector to visualize the the data sent on the SPI bus. I remark that I am only sending the first value of the buffer (master_send[0]) even if I loop trough the whole buffer?&lt;/P&gt;&lt;P&gt;for (count1 = 0; count1 &amp;lt; 2; count1++)&lt;BR /&gt;{&lt;BR /&gt;Pointer = (uint16_t *)&amp;amp;master_send[count1].XS_Spd_In_Data[0];&lt;BR /&gt;Dspi_status = DSPI_MasterTransfer(INST_DSPI1, Pointer, &amp;amp;master_receive[0], NUMBER_OF_FRAMES);&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;Do you have any idea about the source of this problem? Thank you in advance.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Capture d’écran 2021-07-05 222610.png" style="width: 921px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/148825iA768CED517733A8F/image-size/large?v=v2&amp;amp;px=999" role="button" title="Capture d’écran 2021-07-05 222610.png" alt="Capture d’écran 2021-07-05 222610.png" /&gt;&lt;/span&gt;&amp;nbsp;&lt;/P&gt;&lt;BLOCKQUOTE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;/*&lt;BR /&gt;* Copyright 2017 NXP&lt;BR /&gt;* All rights reserved.&lt;BR /&gt;*&lt;BR /&gt;* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR&lt;BR /&gt;* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES&lt;BR /&gt;* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.&lt;BR /&gt;* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,&lt;BR /&gt;* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES&lt;BR /&gt;* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR&lt;BR /&gt;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)&lt;BR /&gt;* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,&lt;BR /&gt;* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING&lt;BR /&gt;* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF&lt;BR /&gt;* THE POSSIBILITY OF SUCH DAMAGE.&lt;BR /&gt;*/&lt;BR /&gt;/* ###################################################################&lt;BR /&gt;** Filename : main.c&lt;BR /&gt;** Project : pit_periodic_interrupt_mpc5748g&lt;BR /&gt;** Processor : MPC5748G_324&lt;BR /&gt;** Version : Driver 01.00&lt;BR /&gt;** Compiler : GNU C Compiler&lt;BR /&gt;** Date/Time : 2017-03-15, 12:21, # CodeGen: 6&lt;BR /&gt;** Abstract :&lt;BR /&gt;** Main module.&lt;BR /&gt;** This module contains user's application code.&lt;BR /&gt;** Settings :&lt;BR /&gt;** Contents :&lt;BR /&gt;** No public methods&lt;BR /&gt;**&lt;BR /&gt;** ###################################################################*/&lt;BR /&gt;/*!&lt;BR /&gt;** @file main.c&lt;BR /&gt;** @version 01.00&lt;BR /&gt;** @brief&lt;BR /&gt;** Main module.&lt;BR /&gt;** This module contains user's application code.&lt;BR /&gt;*/&lt;BR /&gt;/*!&lt;BR /&gt;** @addtogroup main_module main module documentation&lt;BR /&gt;** @{&lt;BR /&gt;*/&lt;BR /&gt;/* MODULE main */&lt;BR /&gt;/* Including needed modules to compile this module/procedure */&lt;BR /&gt;#include "Cpu.h"&lt;BR /&gt;#include "pit1.h"&lt;BR /&gt;#include "clockMan1.h"&lt;BR /&gt;#include "pin_mux.h"&lt;BR /&gt;#include "dspi1.h"&lt;BR /&gt;#include "MC20XS4200_Drv.h"&lt;BR /&gt;volatile int exit_code = 0;&lt;/P&gt;&lt;P&gt;typedef union&lt;BR /&gt;{&lt;BR /&gt;uint16_t XS_Spd_In_Data[7];&lt;BR /&gt;struct&lt;BR /&gt;{&lt;BR /&gt;TstIO_eSPD_STATR_In_Bits XS_StartIn; //Start register&lt;BR /&gt;TstIO_eSPD_PWMR_In_Bits XS_PwmIn; //pwm register&lt;BR /&gt;TstIO_eSPD_CONFR_In_Bits XS_ConfIn; //configuration register&lt;BR /&gt;TstIO_eSPD_OCR_In_Bits XS_OcrIn; //ocr register&lt;BR /&gt;TstIO_eSPD_RETRYR_In_Bits XS_RetrayIn;//Retry register&lt;BR /&gt;TstIO_eSPD_GCR_In_Bits XS_GcrIn; //GCR register&lt;BR /&gt;uint16_t XS_CalbIn; //Calibration register&lt;BR /&gt;};&lt;BR /&gt;} XS_SpdInRegsData;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;#define BUFFER_SIZE 7U&lt;BR /&gt;#define NUMBER_OF_FRAMES 7U&lt;BR /&gt;#define TIMEOUT 1000U&lt;BR /&gt;/* User includes (#include below this line is not maintained by Processor Expert) */&lt;BR /&gt;/* This example is setup to work by default with DEVKIT. To use it with other boards&lt;BR /&gt;please comment the following line&lt;BR /&gt;*/&lt;/P&gt;&lt;P&gt;/* Write your local variable definition here */&lt;/P&gt;&lt;P&gt;XS_SpdInRegsData master_send[2]={0};&lt;BR /&gt;uint16_t master_send_cache[7 * 2];&lt;BR /&gt;status_t Dspi_status;&lt;BR /&gt;dspi_transfer_status_t DSp_Busy;&lt;BR /&gt;//uint8_t master_receive[BUFFER_SIZE];&lt;BR /&gt;uint16_t count;&lt;BR /&gt;uint8_t master_receive[BUFFER_SIZE];&lt;BR /&gt;uint8_t slave_send[] = { 1, 2, 3, 4, 5, 6, 7 };&lt;BR /&gt;uint8_t slave_receive[BUFFER_SIZE];&lt;BR /&gt;uint16_t count1 = 0;&lt;BR /&gt;uint16_t count2;&lt;BR /&gt;static uint16_t DutyCycle = 0;&lt;BR /&gt;uint16_t *Pointer = NULL;&lt;BR /&gt;#define DEVKIT&lt;BR /&gt;#ifdef DEVKIT&lt;BR /&gt;#define PORT PTA&lt;BR /&gt;#define LED 10 /* pin PA[10] - LED3 (DS4) on DEV-KIT */&lt;BR /&gt;#else&lt;BR /&gt;#define PORT PTG&lt;BR /&gt;#define LED 2 /* pin PG[2] - LED1 (DS2) on Motherboard */&lt;BR /&gt;#endif&lt;BR /&gt;void PIT_Ch0_IRQHandler(void)&lt;BR /&gt;{&lt;BR /&gt;PINS_DRV_TogglePins(PORT, (1 &amp;lt;&amp;lt; LED));&lt;BR /&gt;PIT_DRV_ClearStatusFlags(INST_PIT1, pit1_ChnConfig0.hwChannel); /* Clear channel 0 interrupt flag */&lt;/P&gt;&lt;P&gt;/* update the the period */&lt;BR /&gt;(void) des_MC20XS4200_PwmUpdate(&amp;amp;master_send[0], DutyCycle);&lt;/P&gt;&lt;P&gt;for (count1 = 0; count1 &amp;lt; 2; count1++)&lt;BR /&gt;{&lt;BR /&gt;Pointer = (uint16_t *)&amp;amp;master_send[count1].XS_Spd_In_Data[0];&lt;BR /&gt;Dspi_status = DSPI_MasterTransfer(INST_DSPI1, Pointer, &amp;amp;master_receive[0], NUMBER_OF_FRAMES);&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;}&lt;BR /&gt;/*!&lt;BR /&gt;\brief The main function for the project.&lt;BR /&gt;\details The startup initialization sequence is the following:&lt;BR /&gt;* - startup asm routine&lt;BR /&gt;* - main()&lt;BR /&gt;*/&lt;BR /&gt;int main(void)&lt;BR /&gt;{&lt;BR /&gt;/*** Processor Expert internal initialization. DON'T REMOVE THIS CODE!!! ***/&lt;BR /&gt;#ifdef PEX_RTOS_INIT&lt;BR /&gt;PEX_RTOS_INIT(); /* Initialization of the selected RTOS. Macro is defined by the RTOS component. */&lt;BR /&gt;#endif&lt;BR /&gt;/*** End of Processor Expert internal initialization. ***/&lt;BR /&gt;/* Initialize clock gate*/&lt;BR /&gt;CLOCK_SYS_Init(g_clockManConfigsArr, CLOCK_MANAGER_CONFIG_CNT,&lt;BR /&gt;g_clockManCallbacksArr, CLOCK_MANAGER_CALLBACK_CNT);&lt;BR /&gt;CLOCK_SYS_UpdateConfiguration(0U, CLOCK_MANAGER_POLICY_AGREEMENT);&lt;/P&gt;&lt;P&gt;/* Initialize and configure pins */&lt;BR /&gt;PINS_DRV_Init(NUM_OF_CONFIGURED_PINS, g_pin_mux_InitConfigArr);&lt;/P&gt;&lt;P&gt;/*&lt;BR /&gt;*&lt;BR /&gt;* Init the DSPI peripheral*/&lt;BR /&gt;/* SPI master configuration: clock speed: 500 kHz, 8 bits/frame, MSB first */&lt;BR /&gt;DSPI_MasterInit(DSPI0_INSTANCE, &amp;amp;dspi1State, &amp;amp;dspi1_MasterInitConfig0);&lt;/P&gt;&lt;P&gt;/* Configure delay between transfer, delay between SCK and PCS and delay between PCS and SCK */&lt;BR /&gt;DSPI_MasterSetDelay(DSPI0_INSTANCE, 1, 1, 1);&lt;/P&gt;&lt;P&gt;/*&lt;BR /&gt;*&lt;BR /&gt;* Init the PIT peripheral*/&lt;BR /&gt;/* Initialize PIT */&lt;BR /&gt;PIT_DRV_Init(INST_PIT1, &amp;amp;pit1_InitConfig);&lt;/P&gt;&lt;P&gt;/* Initialize channel 0 */&lt;BR /&gt;PIT_DRV_InitChannel(INST_PIT1, &amp;amp;pit1_ChnConfig0);&lt;/P&gt;&lt;P&gt;/* Start channel 0 counting */&lt;BR /&gt;PIT_DRV_StartChannel(INST_PIT1, pit1_ChnConfig0.hwChannel);&lt;/P&gt;&lt;P&gt;/* Init */&lt;BR /&gt;DutyCycle = 0;&lt;BR /&gt;/*&lt;BR /&gt;*&lt;BR /&gt;* Init the uart peripheral*/&lt;/P&gt;&lt;P&gt;/* Initialize the master send buffer */&lt;BR /&gt;(void) des_MC20XS4200_Config(&amp;amp;master_send[0]);&lt;/P&gt;&lt;P&gt;/* Send CAFE to test SPI communication */&lt;BR /&gt;for (count1 = 0; count1 &amp;lt; 2; count1++)&lt;BR /&gt;{&lt;BR /&gt;Pointer = (uint16_t *)&amp;amp;master_send[count1].XS_Spd_In_Data[0];&lt;BR /&gt;Dspi_status = DSPI_MasterTransfer(INST_DSPI1,Pointer, &amp;amp;master_receive[0],NUMBER_OF_FRAMES);&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;}&lt;/P&gt;&lt;P&gt;/*** Don't write any code pass this line, or it will be deleted during code generation. ***/&lt;BR /&gt;/*** RTOS startup code. Macro PEX_RTOS_START is defined by the RTOS component. DON'T MODIFY THIS CODE!!! ***/&lt;BR /&gt;#ifdef PEX_RTOS_START&lt;BR /&gt;PEX_RTOS_START(); /* Startup of the selected RTOS. Macro is defined by the RTOS component. */&lt;BR /&gt;#endif&lt;BR /&gt;/*** End of RTOS startup code. ***/&lt;BR /&gt;/*** Processor Expert end of main routine. DON'T MODIFY THIS CODE!!! ***/&lt;BR /&gt;for(;;) {&lt;BR /&gt;if(exit_code != 0) {&lt;BR /&gt;break;&lt;BR /&gt;}&lt;BR /&gt;}&lt;BR /&gt;return exit_code;&lt;BR /&gt;/*** Processor Expert end of main routine. DON'T WRITE CODE BELOW!!! ***/&lt;BR /&gt;} /*** End of main routine. DO NOT MODIFY THIS TEXT!!! ***/&lt;BR /&gt;/* END main */&lt;BR /&gt;/*!&lt;BR /&gt;** @}&lt;BR /&gt;*/&lt;BR /&gt;/*&lt;BR /&gt;** ###################################################################&lt;BR /&gt;**&lt;BR /&gt;** This file was created by Processor Expert 10.1 [05.21]&lt;BR /&gt;** for the NXP C55 series of microcontrollers.&lt;BR /&gt;**&lt;BR /&gt;** ###################################################################&lt;BR /&gt;*/&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 05 Jul 2021 20:32:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/DSPI-interface-issu-while-sending-union-buffer/m-p/1302589#M49</guid>
      <dc:creator>InHome</dc:creator>
      <dc:date>2021-07-05T20:32:52Z</dc:date>
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