topic Re: DDR subsystem register base address in S32G

DDR subsystem register base address

0xEC — Mon, 07 Aug 2023 11:12:41 GMT

Hi everyone,

I have a question about reference manual,

In S32G2RM it says DDR Subsystem base address is 0x403D_0000

but in attachment of reference manual (S32G2_Memory_Map.xlsx) it says DDR Subsystem base address is 0x4038_0000, which one is correct? and also i could not find register for

DDR_PHYA_APBONLY_UCTWRITEONLYSHADOW whose address is 0x40380410.

Could someone help me who were working on DDR subsystem previously?

best,

Re: DDR subsystem register base address

Daniel-Aguirre — Mon, 07 Aug 2023 18:03:20 GMT

Hi,

Can you let us know from which Reference Manual version you are using? Is the memory map taken from this same Reference Manual version?

Also, we cannot find the register you are mentioning under the S32G2 Reference Manual v7, where are you finding it?

Please, let us know.

Re: DDR subsystem register base address

0xEC — Tue, 08 Aug 2023 06:33:08 GMT

hi,
i am using S32G2RM Rev. 4, October 2021,
Yes i got memory map excel file from the same reference manual.
DDR_PHYA_APBONLY_UCTWRITEONLYSHADOW this register is taken from source code of TF-A for s32g2 while trying to initialization of DDR ram, it fails while reading from this register. So i need to know what information exists in this register.

Re: DDR subsystem register base address

0xEC — Tue, 08 Aug 2023 06:52:40 GMT

these are two inconsistent info taken from RM and RM's attachment excel file,

Re: DDR subsystem register base address

Daniel-Aguirre — Wed, 09 Aug 2023 15:28:06 GMT

Hi,

The revision of the Reference Manual is not the latest one, we always recommend using the latest one.

Still, we have found the inconsistency on the latest revision, thanks for your feedback.

We recommend following the Reference Manual as for the base address, but we will confirm which of the 2 is correct or why the inconsistency.

Please, let us know.

Re: DDR subsystem register base address

Daniel-Aguirre — Thu, 10 Aug 2023 15:19:59 GMT

Hi,

We have received the following update on regards of this topic:

DDR SS Reg (reg_grp0) on S32G2 RM Rev.7 is only a register and means DDR_Subsystem base address, the start address is 0x403D_0000.

By the way, 0x4038_0000 is the start address of DWC_DDRPHYA_ACSM0 register and means the DWC_DDRPHYA_ACSM0 base address.

DDRSS_0 on S32G2 RM Rev.7 attached is only a Peripheral description and means DDR subsystem, it includes all DDR PHY registers contents.

So, there represents different meaning on the S32G2 RM and S32G2 RM attached.

As for the "DDR_PHYA_APBONLY_UCTWRITEONLYSHADOW" register, the following is told:

"...although customer has not the information of DDR_PHYA_APBONLY_UCTWRITEONLYSHADOW, it will also not be impacting the usage."

Please, let us know.

Re: DDR subsystem register base address

0xEC — Fri, 11 Aug 2023 07:08:51 GMT

thanks for reply,

I was trying to initialize LPDDR 2GB RAM in custom board and DDR_PHYA_APBONLY_UCTWRITEONLYSHADOW register reading returned 0xFF (means failure) in initialization sequence so i thought to get information about this register in order to understand the fail reason, but after applying initialization code generated by S32DS DDR Tool for 2GB LPDDR according to related RAM parameters, it did not return 0xFF anymore, it fixed now.

best,