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    <title>topic Re: u-boot ddr ram initialization in S32G</title>
    <link>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1690336#M4169</link>
    <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/202062"&gt;@0xEC&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;Ideally, u-boot doesn't initialize the DDR. DDR initialization is performed by the SPL(Secondary Program Loader).&lt;/P&gt;
&lt;P&gt;you can refer more information from here:&amp;nbsp;&lt;A href="https://u-boot.readthedocs.io/en/stable/develop/spl.html" target="_blank"&gt;https://u-boot.readthedocs.io/en/stable/develop/spl.html&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Hope this helps you.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks,&lt;/P&gt;
&lt;P&gt;Mayank s Patel&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Fri, 21 Jul 2023 10:06:42 GMT</pubDate>
    <dc:creator>MayanksPatel</dc:creator>
    <dc:date>2023-07-21T10:06:42Z</dc:date>
    <item>
      <title>u-boot ddr ram initialization</title>
      <link>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1689495#M4162</link>
      <description>&lt;P&gt;hi everyone,&lt;/P&gt;&lt;P&gt;i am working on s32g2 series SoC. I have a53 cores which run embedded linux. i compile linux using yocto build environment which also compiles u-boot and using it on target. i have generic question that how u-boot initialize DDR ram integrated in target? in what order the u-boot functions are called i mean entry point of u-boot?&lt;/P&gt;&lt;P&gt;do you have any suggestion which helps me on understanding of working principles of u-boot, board initalization etc.&lt;/P&gt;&lt;P&gt;thanks in advance&lt;/P&gt;&lt;P&gt;best,&lt;/P&gt;</description>
      <pubDate>Thu, 20 Jul 2023 14:29:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1689495#M4162</guid>
      <dc:creator>0xEC</dc:creator>
      <dc:date>2023-07-20T14:29:43Z</dc:date>
    </item>
    <item>
      <title>Re: u-boot ddr ram initialization</title>
      <link>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1690336#M4169</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/202062"&gt;@0xEC&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;Ideally, u-boot doesn't initialize the DDR. DDR initialization is performed by the SPL(Secondary Program Loader).&lt;/P&gt;
&lt;P&gt;you can refer more information from here:&amp;nbsp;&lt;A href="https://u-boot.readthedocs.io/en/stable/develop/spl.html" target="_blank"&gt;https://u-boot.readthedocs.io/en/stable/develop/spl.html&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Hope this helps you.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks,&lt;/P&gt;
&lt;P&gt;Mayank s Patel&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 21 Jul 2023 10:06:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1690336#M4169</guid>
      <dc:creator>MayanksPatel</dc:creator>
      <dc:date>2023-07-21T10:06:42Z</dc:date>
    </item>
    <item>
      <title>Re: u-boot ddr ram initialization</title>
      <link>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1690493#M4171</link>
      <description>&lt;P&gt;thank you for reply,&lt;/P&gt;&lt;P&gt;i may have misunderstood the concept, but if u-boot does not initialize DDR, so who is responsible for this initalization. i ask this question because i have s32g274a-rdb2 board which has 4GB DDR ram and it works with yocto image that i compile which includes u-boot also, i also have 2GB DDR ram and 4GB DDR ram target custom board. in custom boards, the 2GB one does not boot even u-boot there is no response, in 4GB ram custom board u-boot is booting but after u-boot count down board reset itself. the reason that i think u-boot initialize DDR ram, because of 2GB not responding in serial console.&lt;/P&gt;&lt;P&gt;is there any documents which explain boot sequence of s32g274a in a53 manner? i have lots of nxp documents but none of them explain anything about booting sequence in overview.&lt;/P&gt;&lt;P&gt;best,&lt;/P&gt;</description>
      <pubDate>Fri, 21 Jul 2023 14:35:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1690493#M4171</guid>
      <dc:creator>0xEC</dc:creator>
      <dc:date>2023-07-21T14:35:26Z</dc:date>
    </item>
    <item>
      <title>Re: u-boot ddr ram initialization</title>
      <link>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1692274#M4201</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/202062"&gt;@0xEC&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;The SPL(Secondary program loader.) is the part of u-boot source code.&lt;/P&gt;
&lt;P&gt;Please find the attached document which guides you through the boot sequence for S32G2.&lt;/P&gt;
&lt;P&gt;Also, the current Linux BSP, starting from BSP32, all support ATF(Arm Trusted Firmware) by default, so the bootloader will first load the ATF(Arm Trusted Firmware) into the internal SRAM, and then ATF(Arm Trusted Firmware) will initialize the external DDR, and ATF will be responsible for loading the u-boot code from eMMC/SDcard.&lt;/P&gt;
&lt;P&gt;Hope this helps you.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks,&lt;/P&gt;
&lt;P&gt;Mayank s Patel&lt;/P&gt;</description>
      <pubDate>Tue, 25 Jul 2023 12:28:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1692274#M4201</guid>
      <dc:creator>MayanksPatel</dc:creator>
      <dc:date>2023-07-25T12:28:04Z</dc:date>
    </item>
    <item>
      <title>Re: u-boot ddr ram initialization</title>
      <link>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1692285#M4202</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/204248"&gt;@MayanksPatel&lt;/a&gt;thanks for reply&lt;BR /&gt;I have been investigating on ATF, u-boot and linux kernel booting in yocto image, i partially understood the boot stages thank you for clearance, one thing that i wonder that, i have custom board s32g274a SoC and 2GB DRAM, even if DRAM could not be initialize ATF must be boot up right? and i should see some serial log on uart from ATF? but i could not see anything in this configuration. Do you have any suggestion that may help me?&lt;BR /&gt;Best,&lt;/P&gt;</description>
      <pubDate>Tue, 25 Jul 2023 12:46:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1692285#M4202</guid>
      <dc:creator>0xEC</dc:creator>
      <dc:date>2023-07-25T12:46:58Z</dc:date>
    </item>
    <item>
      <title>Re: u-boot ddr ram initialization</title>
      <link>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1692728#M4214</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/202062"&gt;@0xEC&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;Have you made any changes in ATF Firmware? If yes, Please share it here.&lt;/P&gt;
&lt;P&gt;Please share the BSP version used.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks,&lt;/P&gt;
&lt;P&gt;Mayank s Patel&lt;/P&gt;</description>
      <pubDate>Wed, 26 Jul 2023 06:21:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1692728#M4214</guid>
      <dc:creator>MayanksPatel</dc:creator>
      <dc:date>2023-07-26T06:21:07Z</dc:date>
    </item>
    <item>
      <title>Re: u-boot ddr ram initialization</title>
      <link>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1692750#M4215</link>
      <description>hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/204248"&gt;@MayanksPatel&lt;/a&gt;,&lt;BR /&gt;I did not change anything in ATF fw. My BSP version is 33.0 i think this one is latest BSP in nxp yocto distribution.&lt;BR /&gt;Best,</description>
      <pubDate>Wed, 26 Jul 2023 06:44:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1692750#M4215</guid>
      <dc:creator>0xEC</dc:creator>
      <dc:date>2023-07-26T06:44:49Z</dc:date>
    </item>
    <item>
      <title>Re: u-boot ddr ram initialization</title>
      <link>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1695917#M4265</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/202062"&gt;@0xEC&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;Sorry for taking a long time.&lt;/P&gt;
&lt;P&gt;The u-boot start address will be taken from the variable "&lt;SPAN&gt;CONFIG_SYS_TEXT_BASE&lt;/SPAN&gt;".&lt;/P&gt;
&lt;P&gt;This is available in the board_defconfig file.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;The following changes you need to do in the u-boot to support the custom DDR.&lt;/P&gt;
&lt;P&gt;1. Made changes in the DTS File for DDR memory.&lt;/P&gt;
&lt;P&gt;2.modify CONFIG_SYS_TEXT_BASE variable according to your RAM Start Address.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Hope this helps you.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks,&lt;/P&gt;
&lt;P&gt;Mayank s Patel&lt;/P&gt;</description>
      <pubDate>Mon, 31 Jul 2023 12:36:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1695917#M4265</guid>
      <dc:creator>MayanksPatel</dc:creator>
      <dc:date>2023-07-31T12:36:48Z</dc:date>
    </item>
    <item>
      <title>Re: u-boot ddr ram initialization</title>
      <link>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1695948#M4267</link>
      <description>thanks for reply,&lt;BR /&gt;is this DTS file in u-boot or TF-A source code ?,&lt;BR /&gt;in current situation 4GB DDR ram is running normally as in RDB2 board, but in 2GB version i will try to update DTS file as you mentioned.&lt;BR /&gt;best,</description>
      <pubDate>Mon, 31 Jul 2023 13:14:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1695948#M4267</guid>
      <dc:creator>0xEC</dc:creator>
      <dc:date>2023-07-31T13:14:31Z</dc:date>
    </item>
    <item>
      <title>Re: u-boot ddr ram initialization</title>
      <link>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1696623#M4286</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/202062"&gt;@0xEC&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;update it in the u-boot source code.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Hope this works.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks,&lt;/P&gt;
&lt;P&gt;Mayank s Patel&lt;/P&gt;</description>
      <pubDate>Tue, 01 Aug 2023 09:57:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1696623#M4286</guid>
      <dc:creator>MayanksPatel</dc:creator>
      <dc:date>2023-08-01T09:57:05Z</dc:date>
    </item>
    <item>
      <title>Re: u-boot ddr ram initialization</title>
      <link>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1696774#M4293</link>
      <description>&lt;P&gt;but as you said&lt;BR /&gt;"Also, the current Linux BSP, starting from BSP32, all support ATF(Arm Trusted Firmware) by default, so the bootloader will first load the ATF(Arm Trusted Firmware) into the internal SRAM, and then ATF(Arm Trusted Firmware) will initialize the external DDR,"&lt;BR /&gt;is not it the ATF is responsible to initialization of DDR ram so i think dts file must be in ATF right? but in last reply you said "update in u-boot" i do not see any DDR related things in dtsi in u-boot, but in ATF there are 4 or 5 dtsi file which have lots of peripheral, IP related to SoC. long story short, should dts be ATF instead of u-boot right?&lt;/P&gt;</description>
      <pubDate>Tue, 01 Aug 2023 13:45:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1696774#M4293</guid>
      <dc:creator>0xEC</dc:creator>
      <dc:date>2023-08-01T13:45:55Z</dc:date>
    </item>
    <item>
      <title>Re: u-boot ddr ram initialization</title>
      <link>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1697463#M4310</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/202062"&gt;@0xEC&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;I have raised a query with the internal team and I will get back to you once I get a response on this.&lt;/P&gt;
&lt;P&gt;Thank you for your patience.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks,&lt;/P&gt;
&lt;P&gt;Mayank s Patel&lt;/P&gt;</description>
      <pubDate>Wed, 02 Aug 2023 09:36:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1697463#M4310</guid>
      <dc:creator>MayanksPatel</dc:creator>
      <dc:date>2023-08-02T09:36:20Z</dc:date>
    </item>
    <item>
      <title>Re: u-boot ddr ram initialization</title>
      <link>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1700811#M4384</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/202062"&gt;@0xEC&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;The best way to generate DDR configuration, you have to generate a new DDR configuration code based on your design.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Click the Help button in the S32DS DDR Tool for detailed help information.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;Please find the attached image for your reference.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks,&lt;/P&gt;
&lt;P&gt;Mayank s Patel&lt;/P&gt;</description>
      <pubDate>Tue, 08 Aug 2023 07:16:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1700811#M4384</guid>
      <dc:creator>MayanksPatel</dc:creator>
      <dc:date>2023-08-08T07:16:01Z</dc:date>
    </item>
    <item>
      <title>Re: u-boot ddr ram initialization</title>
      <link>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1700821#M4385</link>
      <description>hi @MayaksPatel,&lt;BR /&gt;Thanks for reply,&lt;BR /&gt;actually i used s32ds to change initialization code for DDR in ATF, and i generate initialization codes and replaced the generated files with old ones which were used for 4GB DDR. but still the 2gb DDR ram version hardware not booting u-boot, it stucks at ATF. i asked other questions to change start address of U-Boot and i found some information which says SYS_TEXT_BASE and SYS_DATA_BASE must be change according to new RAM address range, but i still could not boot u-boot while initialization of DDR ram system stuck, i will try to get help from s32ds DDR tool.&lt;BR /&gt;best,</description>
      <pubDate>Tue, 08 Aug 2023 07:26:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1700821#M4385</guid>
      <dc:creator>0xEC</dc:creator>
      <dc:date>2023-08-08T07:26:56Z</dc:date>
    </item>
    <item>
      <title>Re: u-boot ddr ram initialization</title>
      <link>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1701002#M4394</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/202062"&gt;@0xEC&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Before proceeding further, I need to make sure that all the basic settings are correct.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Please help share the following information:&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;1.Schematic diagram (including S32G DRAM port and LPDDR4 schematic diagram)&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;2.LPDDR4 part number and datasheet&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;3.Screenshot of S32DS “DDR View” page&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;4.Screenshots of "Init", "Diags", "operational", "shmoo" test results in the "Validation" window&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Thanks,&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Mayank s Patel&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 08 Aug 2023 09:43:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1701002#M4394</guid>
      <dc:creator>MayanksPatel</dc:creator>
      <dc:date>2023-08-08T09:43:37Z</dc:date>
    </item>
    <item>
      <title>Re: u-boot ddr ram initialization</title>
      <link>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1701123#M4398</link>
      <description>&lt;P&gt;hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/204248"&gt;@MayanksPatel&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks for reply,&lt;/P&gt;&lt;P&gt;for your questions,&lt;/P&gt;&lt;P&gt;1-) Schematic diagram of DDR Port and LPDDR4 is as follows:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DDR connection1" style="width: 804px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/235553i038DE133DD05A422/image-size/large?v=v2&amp;amp;px=999" role="button" title="MicrosoftTeams-image (2).png" alt="DDR connection1" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;DDR connection1&lt;/span&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DDR connection2" style="width: 589px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/235552iDA3821F47E28E91A/image-size/large?v=v2&amp;amp;px=999" role="button" title="MicrosoftTeams-image (1).png" alt="DDR connection2" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;DDR connection2&lt;/span&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DDR connection3" style="width: 967px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/235554i16E4B516E4AFDF5C/image-size/large?v=v2&amp;amp;px=999" role="button" title="MicrosoftTeams-image.png" alt="DDR connection3" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;DDR connection3&lt;/span&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;2)LPDDR4 part number is&amp;nbsp;&lt;SPAN&gt;&lt;SPAN class=""&gt;MT53D512M32D2, which is same chip but 2GB version used in S32G274-RDB2 board (this board has 4GB RAM whose part number is&amp;nbsp;MT53D1024M32D4)&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN class=""&gt;3)DDR view screen shot is:&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN class=""&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DDR device info" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/235555iD0D04F377C251582/image-size/large?v=v2&amp;amp;px=999" role="button" title="DDR_device_info.png" alt="DDR device info" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;DDR device info&lt;/span&gt;&lt;/span&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN class=""&gt;4) "init", "diags", "operational" and "shmoo" test results screen shots are:&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN class=""&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DDR_Diags_test_result" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/235556i2141582B12568A0B/image-size/large?v=v2&amp;amp;px=999" role="button" title="DDR_Diags_test_result.png" alt="DDR_Diags_test_result" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;DDR_Diags_test_result&lt;/span&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DDR_init_test_result" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/235557i8D69DE0DC983B895/image-size/large?v=v2&amp;amp;px=999" role="button" title="DDR_init_test_result.png" alt="DDR_init_test_result" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;DDR_init_test_result&lt;/span&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DDR_operational_test_result" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/235558i721E7ECEBC7E0C90/image-size/large?v=v2&amp;amp;px=999" role="button" title="DDR_operational_test_result.png" alt="DDR_operational_test_result" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;DDR_operational_test_result&lt;/span&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DDR_shmoo_test" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/235559iE90F0E33B091DB76/image-size/large?v=v2&amp;amp;px=999" role="button" title="DDR_shmoo_test.png" alt="DDR_shmoo_test" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;DDR_shmoo_test&lt;/span&gt;&lt;/span&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN class=""&gt;i changed density per channel parameter to 2GB and by that way all test are passed as you can see in above screen shots,&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN class=""&gt;all information that you want are given, please let me know if you need any additional information,&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Thanks in advance,&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best,&lt;/P&gt;</description>
      <pubDate>Tue, 08 Aug 2023 13:02:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1701123#M4398</guid>
      <dc:creator>0xEC</dc:creator>
      <dc:date>2023-08-08T13:02:08Z</dc:date>
    </item>
    <item>
      <title>Re: u-boot ddr ram initialization</title>
      <link>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1701895#M4403</link>
      <description>to update this thread;&lt;BR /&gt;I have adapted the newly generated init code from DDR RAM tool from S32DS, I debug code via lots of printfs and i got that, in ddr_utils_mmio.c file there is a function call namely get_mail(&amp;amp;mail) which is passed to variable with reference and inside this function, there is an register read which returns 0xFF which means training failure in source code and my ATF stucks after this failure.&lt;BR /&gt;Best,</description>
      <pubDate>Wed, 09 Aug 2023 10:46:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1701895#M4403</guid>
      <dc:creator>0xEC</dc:creator>
      <dc:date>2023-08-09T10:46:18Z</dc:date>
    </item>
    <item>
      <title>Re: u-boot ddr ram initialization</title>
      <link>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1702713#M4423</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/202062"&gt;@0xEC&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;It seems that there is a problem with your configuration, please try the following configuration and share the test results here.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DDR_Configuration.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/235913i250475AF7BA5D408/image-size/medium?v=v2&amp;amp;px=400" role="button" title="DDR_Configuration.png" alt="DDR_Configuration.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt; &lt;/P&gt;</description>
      <pubDate>Thu, 10 Aug 2023 07:09:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1702713#M4423</guid>
      <dc:creator>MayanksPatel</dc:creator>
      <dc:date>2023-08-10T07:09:26Z</dc:date>
    </item>
    <item>
      <title>Re: u-boot ddr ram initialization</title>
      <link>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1702732#M4424</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/204248"&gt;@MayanksPatel&lt;/a&gt;,&lt;BR /&gt;After changing parameter that you describe, it fails even in init test, if i changed Number of Chip Selects used to 1, test passes. the result of configuration suggested by you is as follows:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="mayenkPatelSuggestedConfig.png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/235919i763A12BE94C0046C/image-size/large?v=v2&amp;amp;px=999" role="button" title="mayenkPatelSuggestedConfig.png" alt="mayenkPatelSuggestedConfig.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;best,&lt;/P&gt;</description>
      <pubDate>Thu, 10 Aug 2023 07:35:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1702732#M4424</guid>
      <dc:creator>0xEC</dc:creator>
      <dc:date>2023-08-10T07:35:29Z</dc:date>
    </item>
    <item>
      <title>Re: u-boot ddr ram initialization</title>
      <link>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1702918#M4432</link>
      <description>&lt;P&gt;as i mentioned in previous reply, i changed just number of chip select parameter that you suggest to apply,&lt;/P&gt;&lt;P&gt;it generates init code and i adapted it to TF-A source code and it still could not initialize DDR ram.&lt;/P&gt;&lt;P&gt;i got more detail about the flow, the TF-A returns error code in &lt;STRONG&gt;&lt;EM&gt;ddr_init.c&lt;/EM&gt;&lt;/STRONG&gt; source code in &lt;EM&gt;&lt;STRONG&gt;execute_training(const struct ddrss_config* config)&amp;nbsp;&lt;/STRONG&gt;&lt;/EM&gt;function which calls &lt;STRONG&gt;&lt;EM&gt;wait_firmware_execution()&lt;/EM&gt;&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;and in this function there is an register read&amp;nbsp;&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;STRONG&gt;&lt;EM&gt;*mail = mmio_read_32(DDR_PHYA_APBONLY_UCTWRITEONLYSHADOW);&lt;/EM&gt;&lt;/STRONG&gt;&lt;/DIV&gt;&lt;DIV&gt;which returns 0xFF and in source code comment it says 0x07 is success 0xFF is failure&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="0xEC_0-1691666439883.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/235945i9D7BB1B56792359E/image-size/medium?v=v2&amp;amp;px=400" role="button" title="0xEC_0-1691666439883.png" alt="0xEC_0-1691666439883.png" /&gt;&lt;/span&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/DIV&gt;&lt;DIV&gt;best,&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Thu, 10 Aug 2023 11:20:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/u-boot-ddr-ram-initialization/m-p/1702918#M4432</guid>
      <dc:creator>0xEC</dc:creator>
      <dc:date>2023-08-10T11:20:50Z</dc:date>
    </item>
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