<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: About programming s32g3 nor-flash address issue in S32G</title>
    <link>https://community.nxp.com/t5/S32G/About-programming-s32g3-nor-flash-address-issue/m-p/1679993#M3951</link>
    <description>The doc say fip.bin be programmed to flash, but I think it should be fip.s32, do you agree with me ?</description>
    <pubDate>Sun, 02 Jul 2023 13:53:41 GMT</pubDate>
    <dc:creator>fengxianeric</dc:creator>
    <dc:date>2023-07-02T13:53:41Z</dc:date>
    <item>
      <title>About programming s32g3 nor-flash address issue</title>
      <link>https://community.nxp.com/t5/S32G/About-programming-s32g3-nor-flash-address-issue/m-p/1650726#M3201</link>
      <description>&lt;P&gt;I am programming flash with boot M-core and A-core purpose, according to the&amp;nbsp;AN13750.pdf, touch the address scope 0x0~0x500000, and got failed uboot in flash boot mode, I am wondering the address alignment issue due to ever operating uboot memory layout by ds3.5/ivt gfx tool. The clear question is how to program the correct addresse ?&amp;nbsp; thanks.&lt;/P&gt;</description>
      <pubDate>Tue, 16 May 2023 03:33:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/About-programming-s32g3-nor-flash-address-issue/m-p/1650726#M3201</guid>
      <dc:creator>fengxianeric</dc:creator>
      <dc:date>2023-05-16T03:33:55Z</dc:date>
    </item>
    <item>
      <title>Re: About programming s32g3 nor-flash address issue</title>
      <link>https://community.nxp.com/t5/S32G/About-programming-s32g3-nor-flash-address-issue/m-p/1651391#M3219</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;AN13750 is for S32G2 platform, not for S32G3, which you are using (or it is implied on the title).&lt;/P&gt;
&lt;P&gt;Since the Bootloader is designed for S32G2, we cannot confirm that the functionality will stay the same for S32G3.&lt;/P&gt;
&lt;P&gt;Have you used this AN for an S32G2 platform?&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
      <pubDate>Tue, 16 May 2023 17:13:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/About-programming-s32g3-nor-flash-address-issue/m-p/1651391#M3219</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2023-05-16T17:13:49Z</dc:date>
    </item>
    <item>
      <title>Re: About programming s32g3 nor-flash address issue</title>
      <link>https://community.nxp.com/t5/S32G/About-programming-s32g3-nor-flash-address-issue/m-p/1651773#M3231</link>
      <description>No, my handy hw for s32g3 but the only present reference doc is &amp;lt;AN13750.pdf&amp;gt; in this aspect. Basically I know how to start M7 core manually and failed to load by cold-boot way after programming flash partition by s32flashtool GUI.&lt;BR /&gt;</description>
      <pubDate>Wed, 17 May 2023 06:57:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/About-programming-s32g3-nor-flash-address-issue/m-p/1651773#M3231</guid>
      <dc:creator>fengxianeric</dc:creator>
      <dc:date>2023-05-17T06:57:24Z</dc:date>
    </item>
    <item>
      <title>Re: About programming s32g3 nor-flash address issue</title>
      <link>https://community.nxp.com/t5/S32G/About-programming-s32g3-nor-flash-address-issue/m-p/1653222#M3244</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;Thanks for your feedback.&lt;/P&gt;
&lt;P&gt;Just to be sure, you are successfully implementing the bootloader with the M7 application, once you put the A53 application (linux), you fail to boot, is that correct?&lt;/P&gt;
&lt;P&gt;Also, are you using the out-of-the-box BSP for S32G3?&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
      <pubDate>Thu, 18 May 2023 16:08:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/About-programming-s32g3-nor-flash-address-issue/m-p/1653222#M3244</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2023-05-18T16:08:23Z</dc:date>
    </item>
    <item>
      <title>Re: About programming s32g3 nor-flash address issue</title>
      <link>https://community.nxp.com/t5/S32G/About-programming-s32g3-nor-flash-address-issue/m-p/1653433#M3256</link>
      <description>About the aforementioned part, now I can build bootloader successfully and not sure yet about ivt address ajustment correctness (I clicked button auto ajust in ivt gfx interface). About Linux part, 4 kernel modules (*.ko) and sample program (.elf) already been running with errors. So I doubted on m7 apps running issue.</description>
      <pubDate>Fri, 19 May 2023 01:59:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/About-programming-s32g3-nor-flash-address-issue/m-p/1653433#M3256</guid>
      <dc:creator>fengxianeric</dc:creator>
      <dc:date>2023-05-19T01:59:20Z</dc:date>
    </item>
    <item>
      <title>Re: About programming s32g3 nor-flash address issue</title>
      <link>https://community.nxp.com/t5/S32G/About-programming-s32g3-nor-flash-address-issue/m-p/1653951#M3274</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;Thanks for your feedback.&lt;/P&gt;
&lt;P&gt;We still don't understand, we apologize.&lt;/P&gt;
&lt;P&gt;Which NXP BSP are you using? How are you creating the IVT? Are you following AN13750 step by step?&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
      <pubDate>Fri, 19 May 2023 17:16:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/About-programming-s32g3-nor-flash-address-issue/m-p/1653951#M3274</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2023-05-19T17:16:04Z</dc:date>
    </item>
    <item>
      <title>Re: About programming s32g3 nor-flash address issue</title>
      <link>https://community.nxp.com/t5/S32G/About-programming-s32g3-nor-flash-address-issue/m-p/1654135#M3285</link>
      <description>bsp 35.0 ever built by me and produced fsl-iamge-auto, and IVT I mentioned for the configuration windows within tresos studio to configure bootloader.bin. Yes I followed up AN13750 and actutually refer to it due to being documented for s32g2.</description>
      <pubDate>Sat, 20 May 2023 09:07:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/About-programming-s32g3-nor-flash-address-issue/m-p/1654135#M3285</guid>
      <dc:creator>fengxianeric</dc:creator>
      <dc:date>2023-05-20T09:07:02Z</dc:date>
    </item>
    <item>
      <title>Re: About programming s32g3 nor-flash address issue</title>
      <link>https://community.nxp.com/t5/S32G/About-programming-s32g3-nor-flash-address-issue/m-p/1654992#M3306</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;Thanks for your feedback, have you change the FIP_ALIGN variable as per the bootloader requirement?&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DanielAguirre_0-1684776511641.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/224279i9515B9C8D42092DA/image-size/medium?v=v2&amp;amp;px=400" role="button" title="DanielAguirre_0-1684776511641.png" alt="DanielAguirre_0-1684776511641.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
      <pubDate>Mon, 22 May 2023 17:28:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/About-programming-s32g3-nor-flash-address-issue/m-p/1654992#M3306</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2023-05-22T17:28:58Z</dc:date>
    </item>
    <item>
      <title>Re: About programming s32g3 nor-flash address issue</title>
      <link>https://community.nxp.com/t5/S32G/About-programming-s32g3-nor-flash-address-issue/m-p/1659403#M3418</link>
      <description>Thanks very much.&lt;BR /&gt;I still question how to verify fip.bin workable or not.&lt;BR /&gt;I gave a trial by programming 0x100000 on flash, but failed in booting from flash.&lt;BR /&gt;My actions,&lt;BR /&gt;1. programming .flashimg to flash;&lt;BR /&gt;2. programming 0x100000~0x100000+filesize&lt;BR /&gt;Is it correct way to verify ?</description>
      <pubDate>Tue, 30 May 2023 02:36:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/About-programming-s32g3-nor-flash-address-issue/m-p/1659403#M3418</guid>
      <dc:creator>fengxianeric</dc:creator>
      <dc:date>2023-05-30T02:36:08Z</dc:date>
    </item>
    <item>
      <title>Re: About programming s32g3 nor-flash address issue</title>
      <link>https://community.nxp.com/t5/S32G/About-programming-s32g3-nor-flash-address-issue/m-p/1660127#M3425</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;Thanks for your feedback.&lt;/P&gt;
&lt;P&gt;One way you can verify if the "fip.bin" file is working and the "fips.32" was successfully modified in the BSP image is to create an IVT with the A53_0 core selected as the boot core. This will bypass the need of the bootloader, just leaving the "fip.bin" file to verify.&lt;/P&gt;
&lt;P&gt;We will explain the steps below:&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;Create a new project and select the platform and RTD version.&lt;/LI&gt;
&lt;LI&gt;Under the new project, open Config Tools by selecting the folder and clicking on the blue chip icon (Open S32 Configuration Tools), as shown below.&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DanielAguirre_0-1685467178119.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/225471iBA2F48E12210325E/image-size/medium?v=v2&amp;amp;px=400" role="button" title="DanielAguirre_0-1685467178119.png" alt="DanielAguirre_0-1685467178119.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;Once you have entered Config Tools, you select the IVT tab (The 3 horizontal rectangles stacked up) and configure as follows:&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DanielAguirre_1-1685468439370.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/225472iA97CFD38A7CC19C3/image-size/medium?v=v2&amp;amp;px=400" role="button" title="DanielAguirre_1-1685468439370.png" alt="DanielAguirre_1-1685468439370.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;UL class="lia-list-style-type-disc"&gt;
&lt;LI&gt;As a note, the RAM start pointer and RAM entry pointer should be the ones that your ATF build resulted in. For my specific case, the values shown are the ones that the ATF build gave to me, you need to double check the values with your ATF build (as shown on the AN13750).&lt;/LI&gt;
&lt;LI&gt;For the QSPI parameters, some binaries are already provided under the S32DS installation. You should be able to find them following the path (for both S32DS v3.4 and v3.5):&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;C:\nxp\S32DS.3.4\eclipse\mcu_data\processors\S32G399A\PlatformSDK_S32XX_2022_03\quadspi\default_boot_images\mx25_sim133ddr.bin&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;Once you have created the blob image, you flash it into the embedded NOR Flash and change the boot settings to select the QSPI interface. Once the SD is inserted, you turn on the platform and the BootROM should fetch the "fip.bin" from the NOR Flash, then jump to the SD image.&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
      <pubDate>Tue, 30 May 2023 17:49:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/About-programming-s32g3-nor-flash-address-issue/m-p/1660127#M3425</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2023-05-30T17:49:26Z</dc:date>
    </item>
    <item>
      <title>Re: About programming s32g3 nor-flash address issue</title>
      <link>https://community.nxp.com/t5/S32G/About-programming-s32g3-nor-flash-address-issue/m-p/1660660#M3443</link>
      <description>BTW, I see you attached image for g2 but I am responsible for s32g3, so about addresses issue I still worry about them.</description>
      <pubDate>Wed, 31 May 2023 09:04:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/About-programming-s32g3-nor-flash-address-issue/m-p/1660660#M3443</guid>
      <dc:creator>fengxianeric</dc:creator>
      <dc:date>2023-05-31T09:04:45Z</dc:date>
    </item>
    <item>
      <title>Re: About programming s32g3 nor-flash address issue</title>
      <link>https://community.nxp.com/t5/S32G/About-programming-s32g3-nor-flash-address-issue/m-p/1660928#M3449</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;That is correct. We shown the S32G2 IVT configuration, which is valid for S32G3.&lt;/P&gt;
&lt;P&gt;As said before, the addresses are the ones your ATF build provided. The ones we shown are specific to our build. If you use them as we show them, there could be a possibility that it works, but it might be a low probability.&lt;/P&gt;
&lt;P&gt;You should look for the ATF build log and found what are the addresses that your ATF shown. If you followed AN13750, under the ATF steps, it will explain what you should see under the build logs.&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
      <pubDate>Wed, 31 May 2023 15:30:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/About-programming-s32g3-nor-flash-address-issue/m-p/1660928#M3449</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2023-05-31T15:30:41Z</dc:date>
    </item>
    <item>
      <title>Re: About programming s32g3 nor-flash address issue</title>
      <link>https://community.nxp.com/t5/S32G/About-programming-s32g3-nor-flash-address-issue/m-p/1679993#M3951</link>
      <description>The doc say fip.bin be programmed to flash, but I think it should be fip.s32, do you agree with me ?</description>
      <pubDate>Sun, 02 Jul 2023 13:53:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/About-programming-s32g3-nor-flash-address-issue/m-p/1679993#M3951</guid>
      <dc:creator>fengxianeric</dc:creator>
      <dc:date>2023-07-02T13:53:41Z</dc:date>
    </item>
    <item>
      <title>Re: About programming s32g3 nor-flash address issue</title>
      <link>https://community.nxp.com/t5/S32G/About-programming-s32g3-nor-flash-address-issue/m-p/1680620#M3973</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;The following is told under the AN13750:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DanielAguirre_0-1688400172109.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/230548i5C4D7A3346DAD8B4/image-size/medium?v=v2&amp;amp;px=400" role="button" title="DanielAguirre_0-1688400172109.png" alt="DanielAguirre_0-1688400172109.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;For which, fip.bin file is the one being deployed under the NOR Flash.&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
      <pubDate>Mon, 03 Jul 2023 16:03:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/About-programming-s32g3-nor-flash-address-issue/m-p/1680620#M3973</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2023-07-03T16:03:19Z</dc:date>
    </item>
  </channel>
</rss>

