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    <title>S32GのトピックHow to make LLCE_CAN work on M7 for multiboot (M7/A53)</title>
    <link>https://community.nxp.com/t5/S32G/How-to-make-LLCE-CAN-work-on-M7-for-multiboot-M7-A53/m-p/1663308#M3505</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I use Can_llce_DS_Loopback example and run on M7 and configure LINFlexD_1 to output UART log.&lt;/P&gt;&lt;P&gt;It can run normally only on M7_0.&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;I refer to&amp;nbsp;S32G_Bootloader_V2-2022.1024_eng.pdf to configure bootloader and M7 app (Remove Mcu_Init(), Port_Init(), Platform_Init()).&lt;/LI&gt;&lt;LI&gt;Enable the interrupt for UART1 and LLCE_CAN (LINFLEXD1_IRQn/LLCE0_ICSR14_IRQn/LLCE0_ICSR15_IRQn/LLCE0_ICSR16_IRQn/LLCE0_ICSR17_IRQn/LLCE0_ICSR22_IRQn/LLCE0_ICSR23_IRQn).&lt;/LI&gt;&lt;LI&gt;Configure clock for MCU configuration of M7 app and bootloader.&lt;/LI&gt;&lt;LI&gt;Modify linker_ram.ld. Change the region of int_sram to&amp;nbsp;0x34000000.&lt;/LI&gt;&lt;LI&gt;On A53, remove &lt;SPAN&gt;llce_can.config and&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;llce_logger.config (LinuxBSP_35).&lt;/SPAN&gt;&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;When booting, if I enter uboot, the M7 can run LLCE_CAN loopback example normally.&lt;/P&gt;&lt;P&gt;If A53 is booting into OS, the M7 will stop unexpectedly.&lt;/P&gt;&lt;P&gt;Here are my Questions:&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;What configurations do I check for M7 run normally ?&lt;/LI&gt;&lt;LI&gt;Does it possible to let LLCE_CAN controller 0-7 run on M7 and controller 8-15 run on A53&amp;nbsp;simultaneously ?&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Mon, 05 Jun 2023 08:46:47 GMT</pubDate>
    <dc:creator>Namic</dc:creator>
    <dc:date>2023-06-05T08:46:47Z</dc:date>
    <item>
      <title>How to make LLCE_CAN work on M7 for multiboot (M7/A53)</title>
      <link>https://community.nxp.com/t5/S32G/How-to-make-LLCE-CAN-work-on-M7-for-multiboot-M7-A53/m-p/1663308#M3505</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I use Can_llce_DS_Loopback example and run on M7 and configure LINFlexD_1 to output UART log.&lt;/P&gt;&lt;P&gt;It can run normally only on M7_0.&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;I refer to&amp;nbsp;S32G_Bootloader_V2-2022.1024_eng.pdf to configure bootloader and M7 app (Remove Mcu_Init(), Port_Init(), Platform_Init()).&lt;/LI&gt;&lt;LI&gt;Enable the interrupt for UART1 and LLCE_CAN (LINFLEXD1_IRQn/LLCE0_ICSR14_IRQn/LLCE0_ICSR15_IRQn/LLCE0_ICSR16_IRQn/LLCE0_ICSR17_IRQn/LLCE0_ICSR22_IRQn/LLCE0_ICSR23_IRQn).&lt;/LI&gt;&lt;LI&gt;Configure clock for MCU configuration of M7 app and bootloader.&lt;/LI&gt;&lt;LI&gt;Modify linker_ram.ld. Change the region of int_sram to&amp;nbsp;0x34000000.&lt;/LI&gt;&lt;LI&gt;On A53, remove &lt;SPAN&gt;llce_can.config and&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;llce_logger.config (LinuxBSP_35).&lt;/SPAN&gt;&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;When booting, if I enter uboot, the M7 can run LLCE_CAN loopback example normally.&lt;/P&gt;&lt;P&gt;If A53 is booting into OS, the M7 will stop unexpectedly.&lt;/P&gt;&lt;P&gt;Here are my Questions:&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;What configurations do I check for M7 run normally ?&lt;/LI&gt;&lt;LI&gt;Does it possible to let LLCE_CAN controller 0-7 run on M7 and controller 8-15 run on A53&amp;nbsp;simultaneously ?&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 05 Jun 2023 08:46:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/How-to-make-LLCE-CAN-work-on-M7-for-multiboot-M7-A53/m-p/1663308#M3505</guid>
      <dc:creator>Namic</dc:creator>
      <dc:date>2023-06-05T08:46:47Z</dc:date>
    </item>
    <item>
      <title>Re: How to make LLCE_CAN work on M7 for multiboot (M7/A53)</title>
      <link>https://community.nxp.com/t5/S32G/How-to-make-LLCE-CAN-work-on-M7-for-multiboot-M7-A53/m-p/1663652#M3517</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;The following is provided from our internal team:&lt;/P&gt;
&lt;P&gt;"This case has been tested on BSP30(A53) and LLCE 1.0.1(M7)&lt;/P&gt;
&lt;P&gt;For example,&amp;nbsp;resource LLCE CAN0-CAN7 assigned to M7_0 core, and resource LLCE CAN8-CAN15 assigned to A53 cores&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;Precondition&lt;/STRONG&gt;&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;Multiple core boot is ok, and M7 application runs faster than Linux kernel.&lt;/LI&gt;
&lt;LI&gt;CAN_PE clock shall be the same both on M7 and A53 sides.&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;&lt;STRONG&gt;M7 side:&lt;/STRONG&gt;&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;Load fw on the M7 side not A53&lt;/LI&gt;
&lt;LI&gt;Disable interrupt of LLCE CAN8 ~ LLCE CAN15&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DanielAguirre_0-1685987154170.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/226262iE28D9A04CD29C89B/image-size/medium?v=v2&amp;amp;px=400" role="button" title="DanielAguirre_0-1685987154170.png" alt="DanielAguirre_0-1685987154170.png" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;DanielAguirre_0-1685987154170.png&lt;/span&gt;&lt;/span&gt;&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;Modify the ‘PlatformInitConfig0_PB’ corresponding to ‘llce_platform_init’&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;PlatformInitConfig0_PB:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DanielAguirre_1-1685987154370.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/226263i99FC309B23584C7A/image-size/medium?v=v2&amp;amp;px=400" role="button" title="DanielAguirre_1-1685987154370.png" alt="DanielAguirre_1-1685987154370.png" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;DanielAguirre_1-1685987154370.png&lt;/span&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;llce_platform_init&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DanielAguirre_2-1685987154219.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/226264iFCE2F48655A782B3/image-size/medium?v=v2&amp;amp;px=400" role="button" title="DanielAguirre_2-1685987154219.png" alt="DanielAguirre_2-1685987154219.png" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;DanielAguirre_2-1685987154219.png&lt;/span&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;A53 side:&lt;/STRONG&gt;&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;Enable LLCE CAN feature and specify the location where firmware binaries:&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DanielAguirre_3-1685987154112.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/226265i9C28128E29FCA04F/image-size/medium?v=v2&amp;amp;px=400" role="button" title="DanielAguirre_3-1685987154112.png" alt="DanielAguirre_3-1685987154112.png" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;DanielAguirre_3-1685987154112.png&lt;/span&gt;&lt;/span&gt;&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;Disable firmware loading:&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;~/build_s32g274ardb2/tmp/work/s32g274ardb2-fsl-linux/linux-s32/5.10.41-r0/git/drivers/mfd/llce-core.c&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DanielAguirre_4-1685987154066.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/226266i541E67537FD6BECC/image-size/medium?v=v2&amp;amp;px=400" role="button" title="DanielAguirre_4-1685987154066.png" alt="DanielAguirre_4-1685987154066.png" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;DanielAguirre_4-1685987154066.png&lt;/span&gt;&lt;/span&gt;&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;Comment ‘llce_platform_init’&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;~/build_s32g274ardb2/tmp/work/s32g274ardb2-fsl-linux/linux-s32/5.10.41-r0/git/drivers/mailbox/llce-mailbox.c&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DanielAguirre_5-1685987154228.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/226267iDDB8B83C9DCFEBB1/image-size/medium?v=v2&amp;amp;px=400" role="button" title="DanielAguirre_5-1685987154228.png" alt="DanielAguirre_5-1685987154228.png" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;DanielAguirre_5-1685987154228.png&lt;/span&gt;&lt;/span&gt;&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;Disable interrupt of LLCE CAN0 ~ LLCE CAN7&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;~/build_s32g274ardb2/tmp/work/s32g274ardb2-fsl-linux/linux-s32/5.10.41-r0/git/drivers/mailbox/llce-mailbox.c&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DanielAguirre_6-1685987154131.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/226268i57324645AFCC8FF9/image-size/medium?v=v2&amp;amp;px=400" role="button" title="DanielAguirre_6-1685987154131.png" alt="DanielAguirre_6-1685987154131.png" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;DanielAguirre_6-1685987154131.png&lt;/span&gt;&lt;/span&gt;"&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
      <pubDate>Mon, 05 Jun 2023 17:52:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/How-to-make-LLCE-CAN-work-on-M7-for-multiboot-M7-A53/m-p/1663652#M3517</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2023-06-05T17:52:00Z</dc:date>
    </item>
    <item>
      <title>Re: How to make LLCE_CAN work on M7 for multiboot (M7/A53)</title>
      <link>https://community.nxp.com/t5/S32G/How-to-make-LLCE-CAN-work-on-M7-for-multiboot-M7-A53/m-p/1666570#M3586</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;Thanks for your replies.&lt;/P&gt;&lt;P&gt;I used&amp;nbsp;&lt;SPAN&gt;BSP35(A53) and LLCE 1.0.4(M7).&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;I follow the steps to modify the CAN_PE_CLK on M7 and llce-core.c and llce-mailbox.c on A53.&lt;/P&gt;&lt;P&gt;I also remove LLCE_CAN0~8 and LLCE_CAN11~15 in kernel dtsi file.&lt;/P&gt;&lt;P&gt;I run LLCE_CAN0/LLCE_CAN1 on M7 and enable LLCE_CAN9/LLCE_CAN10 on A53.&lt;/P&gt;&lt;P&gt;The M7 app would stop when A53 booting to login.&lt;/P&gt;&lt;P&gt;What configurations do I missing?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;</description>
      <pubDate>Fri, 09 Jun 2023 07:25:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/How-to-make-LLCE-CAN-work-on-M7-for-multiboot-M7-A53/m-p/1666570#M3586</guid>
      <dc:creator>Namic</dc:creator>
      <dc:date>2023-06-09T07:25:10Z</dc:date>
    </item>
    <item>
      <title>Re: How to make LLCE_CAN work on M7 for multiboot (M7/A53)</title>
      <link>https://community.nxp.com/t5/S32G/How-to-make-LLCE-CAN-work-on-M7-for-multiboot-M7-A53/m-p/1667036#M3599</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;Thanks for your feedback.&lt;/P&gt;
&lt;P&gt;Did you disable the loading of LLCE from Linux side? We did not see it mentioned under the steps you followed.&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
      <pubDate>Fri, 09 Jun 2023 15:24:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/How-to-make-LLCE-CAN-work-on-M7-for-multiboot-M7-A53/m-p/1667036#M3599</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2023-06-09T15:24:19Z</dc:date>
    </item>
    <item>
      <title>Re: How to make LLCE_CAN work on M7 for multiboot (M7/A53)</title>
      <link>https://community.nxp.com/t5/S32G/How-to-make-LLCE-CAN-work-on-M7-for-multiboot-M7-A53/m-p/1667320#M3607</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;Yes, I have disabled LLCE on A53 side.&lt;/P&gt;&lt;P&gt;Please check below changes:&lt;/P&gt;&lt;LI-CODE lang="c"&gt;diff --git a/drivers/mailbox/llce-mailbox.c b/drivers/mailbox/llce-mailbox.c
index 87955a60c0f0..ef16d2713636 100644
--- a/drivers/mailbox/llce-mailbox.c
+++ b/drivers/mailbox/llce-mailbox.c
@@ -736,9 +736,9 @@ static int request_llce_pair_irq(struct llce_mb *mb, struct llce_pair_irq *pair)
 {
        int ret;

-       ret = request_llce_irq(mb, &amp;amp;pair-&amp;gt;irq0);
-       if (ret)
-               return ret;
+       // ret = request_llce_irq(mb, &amp;amp;pair-&amp;gt;irq0);
+       // if (ret)
+       //      return ret;

        ret = request_llce_irq(mb, &amp;amp;pair-&amp;gt;irq8);
        if (ret)
@@ -1982,11 +1982,11 @@ static int llce_mb_probe(struct platform_device *pdev)

        fw_logger_support(mb, &amp;amp;ver);

-       ret = llce_platform_init(dev, mb);
-       if (ret) {
-               dev_err(dev, "Failed to initialize platform\n");
-               goto disable_clk;
-       }
+       // ret = llce_platform_init(dev, mb);
+       // if (ret) {
+       //      dev_err(dev, "Failed to initialize platform\n");
+       //      goto disable_clk;
+       // }

        ret = devm_mbox_controller_register(dev, ctrl);
        if (ret &amp;lt; 0) {
diff --git a/drivers/mfd/llce-core.c b/drivers/mfd/llce-core.c
index a9fe41b25d47..0207aff9632d 100644
--- a/drivers/mfd/llce-core.c
+++ b/drivers/mfd/llce-core.c
@@ -61,7 +61,8 @@ struct llce_core {
        size_t nfrws;
 };

-static bool load_fw = true;
+// static bool load_fw = true;
+static bool load_fw = false;
 module_param(load_fw, bool, 0660);

 static struct device_node *get_sram_node(struct device *dev, const char *name)&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 12 Jun 2023 00:46:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/How-to-make-LLCE-CAN-work-on-M7-for-multiboot-M7-A53/m-p/1667320#M3607</guid>
      <dc:creator>Namic</dc:creator>
      <dc:date>2023-06-12T00:46:33Z</dc:date>
    </item>
    <item>
      <title>Re: How to make LLCE_CAN work on M7 for multiboot (M7/A53)</title>
      <link>https://community.nxp.com/t5/S32G/How-to-make-LLCE-CAN-work-on-M7-for-multiboot-M7-A53/m-p/1667739#M3618</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;Thanks for your feedback. Does this happen if you also load a simple blink example with PA_06??&lt;/P&gt;
&lt;P&gt;If so, could be that the dtb has not been modified to not map the pins that the M7 is going to use.&lt;/P&gt;
&lt;P&gt;Also, we were looking that you said the following:&lt;/P&gt;
&lt;P&gt;"Modify linker_ram.ld. Change the region of int_sram to&amp;nbsp;0x34000000."&lt;/P&gt;
&lt;P&gt;It means, that you leave the example as it is? Did you not follow the modification mentioned over "S&lt;SPAN&gt;32G_Bootloader_V2-2022.1024_eng.pdf&amp;nbsp;&lt;/SPAN&gt;"?.&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
      <pubDate>Mon, 12 Jun 2023 21:51:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/How-to-make-LLCE-CAN-work-on-M7-for-multiboot-M7-A53/m-p/1667739#M3618</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2023-06-12T21:51:50Z</dc:date>
    </item>
    <item>
      <title>Re: How to make LLCE_CAN work on M7 for multiboot (M7/A53)</title>
      <link>https://community.nxp.com/t5/S32G/How-to-make-LLCE-CAN-work-on-M7-for-multiboot-M7-A53/m-p/1668653#M3649</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;If the above still does not work, we have received the following notice from our internal team:&lt;/P&gt;
&lt;P&gt;"LLCE CAN multi-host support will be added to Linux BSP37"&lt;/P&gt;
&lt;P&gt;We do apologize.&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;
&lt;P&gt;&lt;LI-WRAPPER&gt;&lt;/LI-WRAPPER&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 13 Jun 2023 22:05:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/How-to-make-LLCE-CAN-work-on-M7-for-multiboot-M7-A53/m-p/1668653#M3649</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2023-06-13T22:05:54Z</dc:date>
    </item>
    <item>
      <title>Re: How to make LLCE_CAN work on M7 for multiboot (M7/A53)</title>
      <link>https://community.nxp.com/t5/S32G/How-to-make-LLCE-CAN-work-on-M7-for-multiboot-M7-A53/m-p/1671371#M3705</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I don't load the sample blink example with PA_06.&lt;/P&gt;&lt;P&gt;But I used the UART1 example with multiboot, and it can work well.&lt;/P&gt;&lt;P&gt;For linker_ram.ld, I followed the&amp;nbsp;&lt;SPAN&gt;"S&lt;/SPAN&gt;&lt;SPAN&gt;32G_Bootloader_V2-2022.1024_eng.pdf&lt;/SPAN&gt;&lt;SPAN&gt;" to modify and M7 app cannot run.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;I modified it as below picture and M7 app with UART1 example can work normally.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Namic_0-1686967193524.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/228190i2A8EC1528BD4C04E/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Namic_0-1686967193524.png" alt="Namic_0-1686967193524.png" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;Namic_0-1686967193524.png&lt;/span&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;But I used LLCE_CAN example, the M7 app would&amp;nbsp;&lt;SPAN&gt;stop unexpectedly during A53 booting.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;</description>
      <pubDate>Sat, 17 Jun 2023 02:07:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/How-to-make-LLCE-CAN-work-on-M7-for-multiboot-M7-A53/m-p/1671371#M3705</guid>
      <dc:creator>Namic</dc:creator>
      <dc:date>2023-06-17T02:07:09Z</dc:date>
    </item>
    <item>
      <title>Re: How to make LLCE_CAN work on M7 for multiboot (M7/A53)</title>
      <link>https://community.nxp.com/t5/S32G/How-to-make-LLCE-CAN-work-on-M7-for-multiboot-M7-A53/m-p/1671372#M3706</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;For the linux BSP37, when can I download it ?&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;</description>
      <pubDate>Sat, 17 Jun 2023 02:12:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/How-to-make-LLCE-CAN-work-on-M7-for-multiboot-M7-A53/m-p/1671372#M3706</guid>
      <dc:creator>Namic</dc:creator>
      <dc:date>2023-06-17T02:12:24Z</dc:date>
    </item>
    <item>
      <title>Re: How to make LLCE_CAN work on M7 for multiboot (M7/A53)</title>
      <link>https://community.nxp.com/t5/S32G/How-to-make-LLCE-CAN-work-on-M7-for-multiboot-M7-A53/m-p/1672125#M3727</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;For what we can see, it seems to be planned sometime in 2023 Q3. This can be moved into Q4 if required but seems Q3 is the plan.&lt;/P&gt;&lt;P&gt;If more information is required on this regard, help us contact your local NXP FAE, for them to provide you with the required release once it is available.&lt;/P&gt;&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
      <pubDate>Mon, 19 Jun 2023 17:26:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/How-to-make-LLCE-CAN-work-on-M7-for-multiboot-M7-A53/m-p/1672125#M3727</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2023-06-19T17:26:30Z</dc:date>
    </item>
    <item>
      <title>Re: How to make LLCE_CAN work on M7 for multiboot (M7/A53)</title>
      <link>https://community.nxp.com/t5/S32G/How-to-make-LLCE-CAN-work-on-M7-for-multiboot-M7-A53/m-p/1711562#M4567</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; &lt;SPAN&gt;I have the same problem. Have you solved this problem?&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 25 Aug 2023 15:34:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/How-to-make-LLCE-CAN-work-on-M7-for-multiboot-M7-A53/m-p/1711562#M4567</guid>
      <dc:creator>ShenYi</dc:creator>
      <dc:date>2023-08-25T15:34:01Z</dc:date>
    </item>
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