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    <title>topic S32G2 PFE-ETH Doubts in S32G</title>
    <link>https://community.nxp.com/t5/S32G/S32G2-PFE-ETH-Doubts/m-p/1650397#M3192</link>
    <description>&lt;P&gt;Hi ,&lt;/P&gt;&lt;P&gt;We are configuring PFE_MAC0/1/2 on M7.&lt;/P&gt;&lt;P&gt;are the below API's are correct or wrong?? please correct me.&lt;/P&gt;&lt;P&gt;1# HIF:&lt;/P&gt;&lt;P&gt;Can_Llce_Init_PfeIf(PFE_PHY_IF_ID_HIF3);&amp;nbsp; -- As 3 MACs are using then 2 different MACs need to use ?? HIF0/1/2 to PFE_MAC0/1/2 respectively -- please correct me if i am right or wrong.&lt;/P&gt;&lt;P&gt;2# Avtp or UDP need to use ??&amp;nbsp; my understanding is UDP API's. please correct me. with respective with HIF.&lt;/P&gt;&lt;P&gt;SampleApp_ConfigFilter_Avtp(PFE_PHY_IF_ID_HIF3, PFE_PHY_IF_ID_EMAC0);&lt;BR /&gt;SampleApp_ConfigFilter_Avtp(PFE_PHY_IF_ID_HIF3, PFE_PHY_IF_ID_EMAC1);&lt;BR /&gt;SampleApp_ConfigFilter_Avtp(PFE_PHY_IF_ID_HIF3, PFE_PHY_IF_ID_EMAC2);&lt;/P&gt;&lt;P&gt;SampleApp_ConfigFilter_Udp(PFE_PHY_IF_ID_HIF3, PFE_PHY_IF_ID_EMAC0);&lt;BR /&gt;SampleApp_ConfigFilter_Avtp(PFE_PHY_IF_ID_HIF3, PFE_PHY_IF_ID_EMAC1);&lt;BR /&gt;SampleApp_ConfigFilter_Udp(PFE_PHY_IF_ID_HIF3, PFE_PHY_IF_ID_EMAC2);&lt;/P&gt;&lt;P&gt;#3: Which of the destination address are correct ??&amp;nbsp;&lt;BR /&gt;//uint8 dstMacAddr[] = { 0xE4, 0x54, 0xE8, 0xBC, 0xB8, 0x88 };&lt;BR /&gt;uint8 dstMacAddr[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };&lt;/P&gt;&lt;P&gt;In the configuration default src_addrr(66:55:44:33:22:11) and dest_addr(ff:ff:ff:ff:ff:ff) is it correct ??&amp;nbsp;&lt;/P&gt;&lt;P&gt;#4: We like to slow path ETh communication are these below APIs are correct or do we need to use ??&lt;BR /&gt;ProvideTxBufferResult = Eth_43_PFE_ProvideTxBuffer(ethCtrl, 0U, &amp;amp;BufferIndex, &amp;amp;bufPtr, &amp;amp;LengthInBytes);&lt;BR /&gt;&lt;BR /&gt;Eth_43_PFE_Transmit(ethCtrl, BufferIndex, 0x0806, TRUE, LengthInBytes, dstMacAddr);&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Viswanath K&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Mon, 15 May 2023 14:28:25 GMT</pubDate>
    <dc:creator>viswa_kondapall</dc:creator>
    <dc:date>2023-05-15T14:28:25Z</dc:date>
    <item>
      <title>S32G2 PFE-ETH Doubts</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-PFE-ETH-Doubts/m-p/1650397#M3192</link>
      <description>&lt;P&gt;Hi ,&lt;/P&gt;&lt;P&gt;We are configuring PFE_MAC0/1/2 on M7.&lt;/P&gt;&lt;P&gt;are the below API's are correct or wrong?? please correct me.&lt;/P&gt;&lt;P&gt;1# HIF:&lt;/P&gt;&lt;P&gt;Can_Llce_Init_PfeIf(PFE_PHY_IF_ID_HIF3);&amp;nbsp; -- As 3 MACs are using then 2 different MACs need to use ?? HIF0/1/2 to PFE_MAC0/1/2 respectively -- please correct me if i am right or wrong.&lt;/P&gt;&lt;P&gt;2# Avtp or UDP need to use ??&amp;nbsp; my understanding is UDP API's. please correct me. with respective with HIF.&lt;/P&gt;&lt;P&gt;SampleApp_ConfigFilter_Avtp(PFE_PHY_IF_ID_HIF3, PFE_PHY_IF_ID_EMAC0);&lt;BR /&gt;SampleApp_ConfigFilter_Avtp(PFE_PHY_IF_ID_HIF3, PFE_PHY_IF_ID_EMAC1);&lt;BR /&gt;SampleApp_ConfigFilter_Avtp(PFE_PHY_IF_ID_HIF3, PFE_PHY_IF_ID_EMAC2);&lt;/P&gt;&lt;P&gt;SampleApp_ConfigFilter_Udp(PFE_PHY_IF_ID_HIF3, PFE_PHY_IF_ID_EMAC0);&lt;BR /&gt;SampleApp_ConfigFilter_Avtp(PFE_PHY_IF_ID_HIF3, PFE_PHY_IF_ID_EMAC1);&lt;BR /&gt;SampleApp_ConfigFilter_Udp(PFE_PHY_IF_ID_HIF3, PFE_PHY_IF_ID_EMAC2);&lt;/P&gt;&lt;P&gt;#3: Which of the destination address are correct ??&amp;nbsp;&lt;BR /&gt;//uint8 dstMacAddr[] = { 0xE4, 0x54, 0xE8, 0xBC, 0xB8, 0x88 };&lt;BR /&gt;uint8 dstMacAddr[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };&lt;/P&gt;&lt;P&gt;In the configuration default src_addrr(66:55:44:33:22:11) and dest_addr(ff:ff:ff:ff:ff:ff) is it correct ??&amp;nbsp;&lt;/P&gt;&lt;P&gt;#4: We like to slow path ETh communication are these below APIs are correct or do we need to use ??&lt;BR /&gt;ProvideTxBufferResult = Eth_43_PFE_ProvideTxBuffer(ethCtrl, 0U, &amp;amp;BufferIndex, &amp;amp;bufPtr, &amp;amp;LengthInBytes);&lt;BR /&gt;&lt;BR /&gt;Eth_43_PFE_Transmit(ethCtrl, BufferIndex, 0x0806, TRUE, LengthInBytes, dstMacAddr);&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Viswanath K&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 15 May 2023 14:28:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-PFE-ETH-Doubts/m-p/1650397#M3192</guid>
      <dc:creator>viswa_kondapall</dc:creator>
      <dc:date>2023-05-15T14:28:25Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2 PFE-ETH Doubts</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-PFE-ETH-Doubts/m-p/1655323#M3321</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/152991"&gt;@viswa_kondapall&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;1. Only one HIF can be used with M7_0, HIF3 is combined with LLCE.&lt;/P&gt;
&lt;P&gt;2. Both if them can be used it depends on your CAN2ETH routing table configuration.&lt;/P&gt;
&lt;P&gt;3. src/dest MAC address in AVTP/UDP&amp;nbsp; also depends on your configuration.&lt;/P&gt;
&lt;P&gt;4. If you want to know how to use PFE driver, please refer to PFE MCAL example and documentation.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Hope this helps.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks,&lt;/P&gt;
&lt;P&gt;Mayank s Patel&lt;/P&gt;</description>
      <pubDate>Tue, 23 May 2023 06:14:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-PFE-ETH-Doubts/m-p/1655323#M3321</guid>
      <dc:creator>MayanksPatel</dc:creator>
      <dc:date>2023-05-23T06:14:02Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2 PFE-ETH Doubts</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-PFE-ETH-Doubts/m-p/1655354#M3322</link>
      <description>&lt;P&gt;Hi Mayank,&lt;/P&gt;&lt;P&gt;Thank you for the reply. It helps. Understood. One point not got clarity is :&lt;/P&gt;&lt;P&gt;Each MAC should have 1 HIF is that correct. Like for Emac0-HIF0/EMAC1-HIF1/EMAC2-HIF2 - or who it is ??&lt;/P&gt;&lt;P&gt;I referred documents - not got clarity or i am not able to understand.&amp;nbsp;&lt;/P&gt;&lt;P&gt;AVTP/UDP:&lt;/P&gt;&lt;P&gt;We are switching to UDP only and going unique (can we keep our unique -- is that anything predefined in&amp;nbsp; PFE-Firmware/driver)MAC-ID's - but IP address are same 127.0.01.&amp;nbsp;&lt;/P&gt;&lt;P&gt;regards,&lt;/P&gt;&lt;P&gt;Viswa&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 23 May 2023 06:44:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-PFE-ETH-Doubts/m-p/1655354#M3322</guid>
      <dc:creator>viswa_kondapall</dc:creator>
      <dc:date>2023-05-23T06:44:34Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2 PFE-ETH Doubts</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-PFE-ETH-Doubts/m-p/1655766#M3332</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/152991"&gt;@viswa_kondapall&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;DIV id="bodyDisplay_1" class="lia-message-body lia-component-message-view-widget-body lia-component-body-signature-highlight-escalation lia-component-message-view-widget-body-signature-highlight-escalation"&gt;
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&lt;P&gt;&lt;SPAN&gt;"Each MAC should have 1 HIF is that correct. Like for Emac0-HIF0/EMAC1-HIF1/EMAC2-HIF2 - or who it is ?"&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;No, we never documented that HIF should be combined with one specific EMAC. Where did you get this information???&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;For PFE MCAL driver slow path, you can only use one HIF in M7_0.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;"We are switching to UDP only and going unique (can we keep our unique -- is that anything predefined in&amp;nbsp; PFE-Firmware/driver)MAC-ID's - but IP address are same 127.0.01.&amp;nbsp;"&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;No, there is no defined in PFE FW. you can do a test if you change the src/dest MAC address in UDP/AVTP.&amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Thanks,&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Mayank s Patel&lt;/SPAN&gt;&lt;/P&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;DIV class="lia-panel lia-panel-standard MessageTagsTaplet Chrome lia-component-message-view-widget-tags"&gt;
&lt;DIV class="lia-decoration-border"&gt;
&lt;DIV class="lia-decoration-border-content"&gt;
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&lt;DIV class="lia-panel-content-wrapper"&gt;
&lt;DIV class="lia-panel-content"&gt;
&lt;DIV class="AddMessageTags lia-message-tags"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
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&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;</description>
      <pubDate>Tue, 23 May 2023 13:17:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-PFE-ETH-Doubts/m-p/1655766#M3332</guid>
      <dc:creator>MayanksPatel</dc:creator>
      <dc:date>2023-05-23T13:17:29Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2 PFE-ETH Doubts</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-PFE-ETH-Doubts/m-p/1656380#M3349</link>
      <description>&lt;P&gt;Hi Mayank,&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;No, we never documented that HIF should be combined with one specific EMAC. Where did you get this information???&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Its understanding from PFE-driver document block diagram.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="viswa_kondapall_0-1684912294586.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/224644i2097352C38B051F9/image-size/medium?v=v2&amp;amp;px=400" role="button" title="viswa_kondapall_0-1684912294586.png" alt="viswa_kondapall_0-1684912294586.png" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;viswa_kondapall_0-1684912294586.png&lt;/span&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;HIF is for connected or it will interface with Host cores. But we are programing CAN2ETH.&lt;/P&gt;&lt;P&gt;CAN packets through LLCE to PFE for this do we need to use HIF-NO COPY.??&lt;/P&gt;&lt;P&gt;#2 :&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;For PFE MCAL driver slow path, you can only use one HIF in M7_0.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;it means HIF is based on CPU ?? if i want 3 MAC2 - PFE_MAC0/1/2 then HIF3 only has to for all MACs ?? or how to ??&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Viswanath K&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 24 May 2023 07:28:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-PFE-ETH-Doubts/m-p/1656380#M3349</guid>
      <dc:creator>viswa_kondapall</dc:creator>
      <dc:date>2023-05-24T07:28:08Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2 PFE-ETH Doubts</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-PFE-ETH-Doubts/m-p/1656537#M3350</link>
      <description>&lt;P&gt;Hi Mayank,&lt;/P&gt;&lt;P&gt;• Slow path forwarding is a combination of two termination traffic flows. The received&lt;BR /&gt;frame is passed to the Host stack which decides to forward the frame to another PFE&lt;BR /&gt;Physical Interface.&lt;/P&gt;&lt;P&gt;• Fast path forwarding is a configurable offload of the Host core stack. The frames&lt;BR /&gt;are forwarded between the Physical Interfaces according to configured rules without&lt;BR /&gt;involving the Host cores.&lt;/P&gt;&lt;P&gt;Difference of this : Please correct me is my understanding is right or not ??????/&lt;/P&gt;&lt;P&gt;Can_Llce_Init_PfeIf(PFE_PHY_IF_ID_HIF3);&amp;nbsp; Slow path&amp;nbsp;&lt;/P&gt;&lt;P&gt;Can_Llce_Init_PfeIf(PFE_PHY_IF_ID_EMAC2); Fast path&amp;nbsp;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 24 May 2023 09:56:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-PFE-ETH-Doubts/m-p/1656537#M3350</guid>
      <dc:creator>viswa_kondapall</dc:creator>
      <dc:date>2023-05-24T09:56:56Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2 PFE-ETH Doubts</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-PFE-ETH-Doubts/m-p/1656567#M3351</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/152991"&gt;@viswa_kondapall&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;Why do you want to enable all three ports of PFE? On an M7_0 core only one interface you can configure.&lt;/P&gt;
&lt;P&gt;You can follow the GUIDE TO ENABLE PFE and from EB Tresos you can configure only one HIF port.&lt;/P&gt;
&lt;P&gt;for receive CAN Packets from LLCE to PFE you need to configure the AUX interface from the EB Tresos. To enable AUX Interface you need to configure new Ethernet_Controller in EB Tresos.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Hope this helps.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks,&lt;/P&gt;
&lt;P&gt;Mayank s Patel&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 24 May 2023 10:27:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-PFE-ETH-Doubts/m-p/1656567#M3351</guid>
      <dc:creator>MayanksPatel</dc:creator>
      <dc:date>2023-05-24T10:27:29Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2 PFE-ETH Doubts</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-PFE-ETH-Doubts/m-p/1656581#M3353</link>
      <description>&lt;P&gt;Hi Mayank,&lt;/P&gt;&lt;P&gt;Thank for reply. Very good discussion we are doing.&amp;nbsp;&lt;/P&gt;&lt;P&gt;1. Now i got clarity 1 CPU - 1 HIF.&amp;nbsp; We are want fast path. so i think dont need HOST interface.&lt;/P&gt;&lt;P&gt;2. I dont Want AUX interface. - I think AUX interface is for LLCE CAN packets to A53. through S32_PFE_FW. as per the CAN gateway block diagram. We configured to EMAC0-2 - as per PFE0-2 respectively.&lt;/P&gt;&lt;P&gt;3. Could you please review my point for the Slow path to fast path.&lt;/P&gt;&lt;P&gt;• Slow path forwarding is a combination of two termination traffic flows. The received&lt;BR /&gt;frame is passed to the Host stack which decides to forward the frame to another PFE&lt;BR /&gt;Physical Interface.&lt;/P&gt;&lt;P&gt;• Fast path forwarding is a configurable offload of the Host core stack. The frames&lt;BR /&gt;are forwarded between the Physical Interfaces according to configured rules without&lt;BR /&gt;involving the Host cores.&lt;/P&gt;&lt;P&gt;Difference of this : Please correct me is my understanding is right or not ??????/&lt;/P&gt;&lt;P&gt;Can_Llce_Init_PfeIf(PFE_PHY_IF_ID_HIF3);&amp;nbsp; Slow path&amp;nbsp;&lt;/P&gt;&lt;P&gt;Can_Llce_Init_PfeIf(PFE_PHY_IF_ID_EMAC2); Fast path&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;regards,&lt;/P&gt;&lt;P&gt;Viswa&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 24 May 2023 10:52:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-PFE-ETH-Doubts/m-p/1656581#M3353</guid>
      <dc:creator>viswa_kondapall</dc:creator>
      <dc:date>2023-05-24T10:52:55Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2 PFE-ETH Doubts</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-PFE-ETH-Doubts/m-p/1657540#M3373</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/152991"&gt;@viswa_kondapall&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;For Slow Path, host core intervention is needed and packet validation and forwarding will be performed by the host cores. (M7&amp;lt;-&amp;gt;HIFx&amp;lt;-&amp;gt;Emacx).&lt;/P&gt;
&lt;P&gt;For Fast Path, PFE firmware will validate the packet to the destination without the involvement of host cores.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Forwarding will decide based on the configured routing table using FCI libraries.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Hope this helps.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks,&lt;/P&gt;
&lt;P&gt;Mayank s Patel&lt;/P&gt;</description>
      <pubDate>Thu, 25 May 2023 09:22:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-PFE-ETH-Doubts/m-p/1657540#M3373</guid>
      <dc:creator>MayanksPatel</dc:creator>
      <dc:date>2023-05-25T09:22:56Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2 PFE-ETH Doubts</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-PFE-ETH-Doubts/m-p/1657591#M3374</link>
      <description>&lt;P&gt;Hi Mayank,&lt;/P&gt;&lt;P&gt;Could you please conclude it with my previous message.&lt;/P&gt;&lt;P&gt;Can_Llce_Init_PfeIf(PFE_PHY_IF_ID_EMAC2); -- can we do like this for fast path instead if HIF&lt;/P&gt;&lt;P&gt;Can_Llce_Init_PfeIf(PFE_PHY_IF_ID_HIF3).&lt;/P&gt;&lt;P&gt;SampleApp_ConfigFilter_Udp(PFE_PHY_IF_ID_HIF3, PFE_PHY_IF_ID_EMAC2); instead of this&amp;nbsp;&lt;/P&gt;&lt;P&gt;SampleApp_ConfigFilter_Udp(PFE_PHY_IF_ID_EMAC2, PFE_PHY_IF_ID_EMAC2); is this okay ??&lt;/P&gt;&lt;P&gt;We are already done CAN2ETH/ETH2CAN configuration, routing table , MAC address and ip address.&lt;/P&gt;&lt;P&gt;regards,&lt;/P&gt;&lt;P&gt;Viswanath K&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Viswa&lt;/P&gt;</description>
      <pubDate>Thu, 25 May 2023 10:07:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-PFE-ETH-Doubts/m-p/1657591#M3374</guid>
      <dc:creator>viswa_kondapall</dc:creator>
      <dc:date>2023-05-25T10:07:54Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2 PFE-ETH Doubts</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-PFE-ETH-Doubts/m-p/1659595#M3420</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/152991"&gt;@viswa_kondapall&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;Sorry for the delay.&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;&lt;SPAN class=""&gt;you can not call this function like that "Can_Llce_Init_PfeIf(PFE_PHY_IF_ID_EMAC2)" and can't configure a fast path and a slow path using the APIs mentioned by you.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;You need to create rules into the routing table using FCI APis from the host cores. Once you configure the rules, by default PFE Firmware will forward traffic by looking at entries into the routing table.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Hope this is clear.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks,&lt;/P&gt;
&lt;P&gt;Mayank s Patel&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 30 May 2023 07:25:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-PFE-ETH-Doubts/m-p/1659595#M3420</guid>
      <dc:creator>MayanksPatel</dc:creator>
      <dc:date>2023-05-30T07:25:47Z</dc:date>
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