topic Re: S32G STM Question in S32G

S32G STM Question

Siyan — Fri, 14 Apr 2023 07:59:02 GMT

Hi, NXP Experts,

Q1: What's the meaning of " One STM instance (STM_7) is tied to Timestamp", how does it works?

Q2: Is "STM_TS" have any differences with other STM instances?

Re: S32G STM Question

Daniel-Aguirre — Fri, 14 Apr 2023 19:43:25 GMT

Hi,

Below will be some comments on regards of your questions:

Q1 >> What's the meaning of " One STM instance (STM_7) is tied to Timestamp", how does it works?

A1 >> This is related to the "CAN_TS_CNT_SEL" bit available under the TIMESTAMP_CONTROL_REGISTER, which Table 394 from the reference manual [Page 2443, S32G2 Reference Manual, Rev. 6, 11/2022] describes:

It means STM_7 can be used to enable timestamp on CAN.

Q2 >> Is "STM_TS" have any differences with other STM instances?

A2 >> Should be related to the timestamp selection of STM_7. If it is selected as the timestamp source, the memory map to configure the timer should be the one under STM_TS register description.

Please, let us know if this information was helpful or not.

Re: S32G STM Question

Siyan — Wed, 19 Apr 2023 00:48:44 GMT

Hi, Daniel,
I can't fully understand the A2 content. Could you explain it by other aspects. Thank you.

Re: S32G STM Question

Daniel-Aguirre — Wed, 19 Apr 2023 15:17:13 GMT

Hi,

Thanks for your feedback. Below will be a different approach for A2.

STM_TS should be the configuration registers [Chapter 40.3, Page 1896, S32G2 Reference Manual, Rev. 6, 11/2022] to be used for STM_7 if STM_7 is selected as a Timestamp source as mentioned on the Table 394 of the S32G2 Reference Manual.

Please, let us know.

Re: S32G STM Question

Siyan — Thu, 20 Apr 2023 00:59:25 GMT

Hi, Daniel,

Does that mean if STM_7 is selected as the Timestamp source, it must be configured through the STM_TS register and configuration through the STM_7 register has no effect. And if STM_7 is not selected as the Timestamp source, STM_7 and STM_TS can be used as two separate timers.

Re: S32G STM Question

Daniel-Aguirre — Fri, 21 Apr 2023 15:32:32 GMT

Hi,

We apologize for our delay, we sent this inquiry to the internal to team to be sure of the provided information. The comment from the internal team is provided below:

"STM_7 and STM_TS are separate timer modules and have no relationship. STM_7 is tied to timestamp and can be configured as a timestamp resource via the TIMESTAMP_CONTROL_REGISTER in the SRC. "

For which we apologize for the comments provided before, it seems STM_7 and STM_TS are not related whatsoever. STM_7 is to be configured under the STM_7 registers with or without Timestamp, for what the internal team has provided.

Again, we apologize, please let us know.

Re: S32G STM Question

jmsc — Fri, 12 May 2023 07:53:54 GMT

Hi @Daniel-Aguirre ,

Could you depict what STM_TS is intended for? In the S32GRM i don't see any special difference among this and the other STM_x. What i saw is STM_TS is in another memory map region.

In addition, S32DS clock source diagram does not provide info about what clock sources drives this STM_TS. However S32GRM claims STM timers are driven by same clock source so we can assume STM_TS timer is driven by the same clock source than other STM_x timers.

Why the TS suffix for this STM? Is tied to a peripheral to make some kind of timestamp like STM_7 has the feature to make timestamp for FlexCAN?

Thank you.

Re: S32G STM Question

Daniel-Aguirre — Fri, 12 May 2023 15:28:14 GMT

Hi,

The following is told from our internal team:

"STM_TS and STM_0~7 just have different interrupt design. for STM_TS, the interrupt is off-chassis. I didn't see any other differences between STM_TS and STM_0~7."

Please, let us know.