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    <title>S32GのトピックRe: Update IVT in RAM failed?</title>
    <link>https://community.nxp.com/t5/S32G/Update-IVT-in-RAM-failed/m-p/1615691#M2473</link>
    <description>&lt;P&gt;&lt;SPAN&gt;Correction: The default of "&lt;/SPAN&gt;&lt;SPAN&gt;int_sram_no_cachable" is&amp;nbsp;(ORIGIN=0x34500000, LENGTH=00100000)。&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Wed, 15 Mar 2023 12:04:59 GMT</pubDate>
    <dc:creator>bookar</dc:creator>
    <dc:date>2023-03-15T12:04:59Z</dc:date>
    <item>
      <title>Update IVT in RAM failed?</title>
      <link>https://community.nxp.com/t5/S32G/Update-IVT-in-RAM-failed/m-p/1613610#M2438</link>
      <description>&lt;P&gt;I am working on S32G m7 core, with S32DS。&amp;nbsp;&lt;/P&gt;&lt;P&gt;to satrtup from SD card, I modified the .ld file acording to &amp;lt;S32G-GOLDBOX-SW-UG&amp;gt; page 19, and then I found that the uart interrupt handler dont sevice correctly。&lt;/P&gt;&lt;P&gt;It seem's that the&amp;nbsp;IntCtrl_Ip_InstallHandler interface dont install the handler correctly, and the default undefined_handler will be called, instead of the expected handler that installed by&amp;nbsp;IntCtrl_Ip_InstallHandler。&lt;/P&gt;&lt;P&gt;Is that caused by cache?&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 13 Mar 2023 02:54:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Update-IVT-in-RAM-failed/m-p/1613610#M2438</guid>
      <dc:creator>bookar</dc:creator>
      <dc:date>2023-03-13T02:54:32Z</dc:date>
    </item>
    <item>
      <title>Re: Update IVT in RAM failed?</title>
      <link>https://community.nxp.com/t5/S32G/Update-IVT-in-RAM-failed/m-p/1614362#M2454</link>
      <description>&lt;P&gt;Hi,&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Could you provide us with what S32DS/RTD version you are working with? Also, are you working with any NXP board?&lt;/P&gt;
&lt;P&gt;Following the&amp;nbsp;&lt;SPAN&gt;S32G-GOLDBOX-SW-UG, did you create the example it is provided in there? Did it work?&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Have you tried with other examples? The behavior is the same?&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Please, let us know.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 13 Mar 2023 22:07:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Update-IVT-in-RAM-failed/m-p/1614362#M2454</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2023-03-13T22:07:18Z</dc:date>
    </item>
    <item>
      <title>Re: Update IVT in RAM failed?</title>
      <link>https://community.nxp.com/t5/S32G/Update-IVT-in-RAM-failed/m-p/1614513#M2456</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;Thanks for your reply.&lt;/P&gt;&lt;P&gt;I,m working on GoldBOX, with S32DS version 3.4, RTD&amp;nbsp;&amp;nbsp;version 3.0.2, and SPD version 1.9.0。&lt;/P&gt;&lt;P&gt;I didnt try other project with this ld file, I will try later.&lt;/P&gt;&lt;P&gt;Forgot to mention, with the "int_sram_no_cacheable" area start from 0x34500000 in ld file, everything seem,s to be OK。&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 14 Mar 2023 03:22:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Update-IVT-in-RAM-failed/m-p/1614513#M2456</guid>
      <dc:creator>bookar</dc:creator>
      <dc:date>2023-03-14T03:22:09Z</dc:date>
    </item>
    <item>
      <title>Re: Update IVT in RAM failed?</title>
      <link>https://community.nxp.com/t5/S32G/Update-IVT-in-RAM-failed/m-p/1615175#M2466</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;Thanks for your feedback.&lt;/P&gt;
&lt;P&gt;Just to verify, if "int_sram_no_cachable" is set as the default (ORIGIN=0x35000000, LENGTH=00100000), you see no problem?&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
      <pubDate>Tue, 14 Mar 2023 18:30:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Update-IVT-in-RAM-failed/m-p/1615175#M2466</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2023-03-14T18:30:59Z</dc:date>
    </item>
    <item>
      <title>Re: Update IVT in RAM failed?</title>
      <link>https://community.nxp.com/t5/S32G/Update-IVT-in-RAM-failed/m-p/1615681#M2470</link>
      <description>&lt;P&gt;yes.&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;if "int_sram_no_cachable" is set as the default (ORIGIN=0x35000000, LENGTH=00100000), there is no problem。&lt;/SPAN&gt;&lt;SPAN&gt;the uart interrupt handler installed with IntCtrl_Ip_InstallHandler&amp;nbsp;works well。&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 15 Mar 2023 11:41:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Update-IVT-in-RAM-failed/m-p/1615681#M2470</guid>
      <dc:creator>bookar</dc:creator>
      <dc:date>2023-03-15T11:41:52Z</dc:date>
    </item>
    <item>
      <title>Re: Update IVT in RAM failed?</title>
      <link>https://community.nxp.com/t5/S32G/Update-IVT-in-RAM-failed/m-p/1615691#M2473</link>
      <description>&lt;P&gt;&lt;SPAN&gt;Correction: The default of "&lt;/SPAN&gt;&lt;SPAN&gt;int_sram_no_cachable" is&amp;nbsp;(ORIGIN=0x34500000, LENGTH=00100000)。&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 15 Mar 2023 12:04:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Update-IVT-in-RAM-failed/m-p/1615691#M2473</guid>
      <dc:creator>bookar</dc:creator>
      <dc:date>2023-03-15T12:04:59Z</dc:date>
    </item>
    <item>
      <title>Re: Update IVT in RAM failed?</title>
      <link>https://community.nxp.com/t5/S32G/Update-IVT-in-RAM-failed/m-p/1616197#M2483</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;Thanks for the correction. We were wrong in the value, as you noted.&lt;/P&gt;</description>
      <pubDate>Wed, 15 Mar 2023 21:22:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Update-IVT-in-RAM-failed/m-p/1616197#M2483</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2023-03-15T21:22:10Z</dc:date>
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