S32G2: handling the LLCE AIPS RX and TX

Mohamed_Abdelalim — Tue, 14 Mar 2023 14:41:12 GMT

We are currently working on a custom Firmware for the LLCE on the S32G2, and I have a couple of questions about the AIPS RX and TX modules :

The actual depth of the FIFOs (i.e., how many elements it can hold) is not mentioned in the RM (e.g. LLCE_BLR_OUT_FIFO_n and TX_ACK_FIFO).
I calculated it to be 242 elements, assuming there any reserved memory after the control block,
and that the whole FIFO is 1024 bytes long and the control block is 56 bytes. is this correct?
Is there any Protection method applied on the FIFOs such as ECC that is used on the RAMs of the 4 cores? If not, how to guarantee its behaviour?
The actual depth of the TxLUT is not explicitly mentioned, I assume its the same as the RxLUT at 1024 entries, correct?
Is there a way to change the searching priority in TxLUT to refer to another parameter such as time of arrival instead of the CAN ID? If not, and I would like to give priority to another message in the middle of the table, does this mean I will have to pop messages and disregard them until I reach the desired message?

Thanks a lot.

topic S32G2: handling the LLCE AIPS RX and TX in S32G