<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: What does PFE HIF_SOFT_RESET need on S32G399A-RDB3 in S32G</title>
    <link>https://community.nxp.com/t5/S32G/What-does-PFE-HIF-SOFT-RESET-need-on-S32G399A-RDB3/m-p/1600646#M2242</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;S32G3 information is still under distribution control. Help us opening a ticket inside the NXP online service or contacting your local NXP representative/FAE, for them to channel it through the correct medium.&lt;/P&gt;
&lt;P&gt;We do apologize for this inconvenience.&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
    <pubDate>Thu, 16 Feb 2023 18:35:14 GMT</pubDate>
    <dc:creator>Daniel-Aguirre</dc:creator>
    <dc:date>2023-02-16T18:35:14Z</dc:date>
    <item>
      <title>What does PFE HIF_SOFT_RESET need on S32G399A-RDB3</title>
      <link>https://community.nxp.com/t5/S32G/What-does-PFE-HIF-SOFT-RESET-need-on-S32G399A-RDB3/m-p/1600614#M2241</link>
      <description>&lt;P&gt;(We are using our own operating system, not Linux)&lt;/P&gt;&lt;P&gt;We ported&amp;nbsp;&lt;SPAN&gt;PFE FW 0.9.X like two years ago and it works fine on RDB2.&amp;nbsp;But it seems not support S32G3. So I downloaded the latest s32g_pfe_*.fw file from version 1.5. But HIF initialization fails because of this “reset timed out” in pfeng_hw.c:&lt;/SPAN&gt;&lt;/P&gt;&lt;PRE&gt;/* SOFT RESET */&lt;BR /&gt;writel(HIF_SOFT_RESET_CMD, base + HIF_SOFT_RESET);&lt;BR /&gt;while (readl(base + HIF_SOFT_RESET) &amp;amp; ~CSR_SW_RESET) {&lt;BR /&gt;    if (++ii &amp;lt; 1000u) {&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; mdelay(1);&lt;BR /&gt;    } else {&lt;BR /&gt;        pr_err("HIF reset timed out.\n");&lt;BR /&gt;        return -ETIMEDOUT;&lt;BR /&gt;    }&lt;BR /&gt;}&lt;/PRE&gt;&lt;P&gt;I’ve configured the SIUL2, CGM, and clock of PFE-MAC2 (I don’t care about PFE-MAC0 and PFE-MAC1 for now. I just want PFE-MAC2 run on RGMII mode) and I don’t know what else I missed. My questions are:&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;What does HIF SOFT RESET require for it to succeed?&lt;/LI&gt;&lt;LI&gt;Do I have to configure the PFE-MAC0 and PFE-MAC1 as well even if they are not used?&lt;/LI&gt;&lt;LI&gt;Although the fw file is the latest, I’m still using our two-year-old PFE code to load it because the new ones in release/bsp35.0 is quite different and will need a lot of time to port to our RTOS. I’ve ported everything under the “on_g3” flag in the pfeng_hw.c. Is it OK?&lt;/LI&gt;&lt;/OL&gt;</description>
      <pubDate>Thu, 16 Feb 2023 17:02:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/What-does-PFE-HIF-SOFT-RESET-need-on-S32G399A-RDB3/m-p/1600614#M2241</guid>
      <dc:creator>ghs_khuang</dc:creator>
      <dc:date>2023-02-16T17:02:28Z</dc:date>
    </item>
    <item>
      <title>Re: What does PFE HIF_SOFT_RESET need on S32G399A-RDB3</title>
      <link>https://community.nxp.com/t5/S32G/What-does-PFE-HIF-SOFT-RESET-need-on-S32G399A-RDB3/m-p/1600646#M2242</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;S32G3 information is still under distribution control. Help us opening a ticket inside the NXP online service or contacting your local NXP representative/FAE, for them to channel it through the correct medium.&lt;/P&gt;
&lt;P&gt;We do apologize for this inconvenience.&lt;/P&gt;
&lt;P&gt;Please, let us know.&lt;/P&gt;</description>
      <pubDate>Thu, 16 Feb 2023 18:35:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/What-does-PFE-HIF-SOFT-RESET-need-on-S32G399A-RDB3/m-p/1600646#M2242</guid>
      <dc:creator>Daniel-Aguirre</dc:creator>
      <dc:date>2023-02-16T18:35:14Z</dc:date>
    </item>
  </channel>
</rss>

