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    <title>topic Re: MMC standard tuning procedure does not work in S32G</title>
    <link>https://community.nxp.com/t5/S32G/MMC-standard-tuning-procedure-does-not-work/m-p/1368279#M219</link>
    <description>&lt;P&gt;Hi ttz766,&lt;/P&gt;
&lt;P&gt;I have tried your sequence, and it works.&lt;/P&gt;
&lt;P&gt;Thanks for your support!&lt;/P&gt;</description>
    <pubDate>Tue, 09 Nov 2021 07:10:03 GMT</pubDate>
    <dc:creator>thomaspham</dc:creator>
    <dc:date>2021-11-09T07:10:03Z</dc:date>
    <item>
      <title>MMC standard tuning procedure does not work</title>
      <link>https://community.nxp.com/t5/S32G/MMC-standard-tuning-procedure-does-not-work/m-p/1336792#M129</link>
      <description>&lt;P&gt;Hello guys,&lt;/P&gt;
&lt;P&gt;I'm debugging standard tuning procedure for MMC card on S32G. After switching the card to HS200 mode, I followed the steps described in the S32G manual as below:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="thomaspham_0-1631095392474.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/155463iD737062D00883C55/image-size/medium?v=v2&amp;amp;px=400" role="button" title="thomaspham_0-1631095392474.png" alt="thomaspham_0-1631095392474.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;I observed these:&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;The MIX_CTRL[EXE_TUNE] bit never get set to 1, it remains 0 the whole time, which is strange.&lt;/LI&gt;
&lt;LI&gt;The data (tuning pattern) is received on the USDHC side, and pattern is correct.&lt;/LI&gt;
&lt;LI&gt;The AUTOCMD12_ERR_STATUS[SMP_CLK_SEL] stays 0 after all, which indicates tuning failed according to the manual.&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;I'd like to ask if anyone face this problem before, or if you have success with tuning procedure on S32G, please drop me a hint.&lt;/P&gt;
&lt;P&gt;Thanks and Best Regards,&lt;/P&gt;
&lt;P&gt;Thomas&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 08 Sep 2021 10:10:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/MMC-standard-tuning-procedure-does-not-work/m-p/1336792#M129</guid>
      <dc:creator>thomaspham</dc:creator>
      <dc:date>2021-09-08T10:10:28Z</dc:date>
    </item>
    <item>
      <title>Re: MMC standard tuning procedure does not work</title>
      <link>https://community.nxp.com/t5/S32G/MMC-standard-tuning-procedure-does-not-work/m-p/1367554#M217</link>
      <description>&lt;P&gt;What you were attempting was the sequence in Rev 3 of the RM, which has been updated in Rev 4.&lt;/P&gt;&lt;P&gt;Rev 4 has still to be formally released but the new sequence is :&lt;/P&gt;&lt;P&gt;By default, lower frequency operation, a fixed sampling clock is used to receive signals on CMD and DAT[3:0]. Before using the&lt;/P&gt;&lt;P&gt;HS200, HS400, SDR104, or SDR50 modes, the Host Driver executes the tuning procedure at the mode switch sequence.&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;Issue uSDHC SW reset, set SYS_CTRL[RSTT] to 1.&lt;/LI&gt;&lt;LI&gt;Set VEND_SPEC[FRC_SDCLK_ON] to 1.&lt;/LI&gt;&lt;LI&gt;Set TUNING_CTRL[DIS_CMD_CHK_FOR_STD_TUNING] to 1.&lt;/LI&gt;&lt;LI&gt;Set AUTOCMD12_ERR_STATUS[EXECUTE_TUNING] to 0.&lt;/LI&gt;&lt;LI&gt;Read AUTOCMD12_ERR_STATUS[EXECUTE_TUNING] to get 0, and then write 1 to clean INT_STATUS[BRR].&lt;/LI&gt;&lt;LI&gt;Start the tuning procedure by setting TUNING_CTRL[STD_TUNING_EN] and&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;AUTOCMD12_ERR_STATUS[EXECUTE_TUNING] to 1.&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;Issue CMD19(SD)/ CMD21(eMMC) with the proper Command Transfer Type (CMD_XFR_TYP) and Auto CMD12 Error&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;Status (AUTOCMD12_ERR_STATUS) settings.&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;Wait for uSDHC BRR (Buffer Read Ready) interrupt signal is 1.&lt;/LI&gt;&lt;LI&gt;Check AUTOCMD12_ERR_STATUS[EXECUTE_TUNING]. If AUTOCMD12_ERR_STATUS[EXECUTE_TUNING] = 1,&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;repeat 5~6. If AUTOCMD12_ERR_STATUS[EXECUTE_TUNING] = 0, standard tuning has completed, or the tuning&lt;/P&gt;&lt;P&gt;has not completed within 40 attempts. The Host Driver might abort this loop if the number of loops exceeds 40 or 150ms&lt;/P&gt;&lt;P&gt;timeout occurs. In this case, a fixed sampling clock should be used, (AUTOCMD12_ERR_STATUS[SMP_CLK_SEL] =&lt;/P&gt;&lt;P&gt;0).&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;Sampling Clock Select, AUTOCMD12_ERR_STATUS[SMP_CLK_SEL] , is valid after&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;AUTOCMD12_ERR_STATUS[EXECUTE_TUNING] has changed from 1 to 0.&lt;/P&gt;&lt;P&gt;AUTOCMD12_ERR_STATUS[SMP_CLK_SEL] = 1, indicates tuning procedure passed.&lt;/P&gt;&lt;P&gt;AUTOCMD12_ERR_STATUS[SMP_CLK_SEL] = 0, indicates tuning procedure failed. The tuning result is applied to the&lt;/P&gt;&lt;P&gt;delay chain, CLK Tuning Control and Status (CLK_TUNE_CTRL_STATUS) [30:16], upon successful tuning procedure&lt;/P&gt;&lt;P&gt;completion.&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;Clear VEND_SPEC[FRC_SDCLK_ON].&lt;/LI&gt;&lt;LI&gt;Set MIX_CTRL[AUTO_TUNE_EN] to 1.&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;Can you try this out&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sun, 07 Nov 2021 17:39:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/MMC-standard-tuning-procedure-does-not-work/m-p/1367554#M217</guid>
      <dc:creator>ttz766</dc:creator>
      <dc:date>2021-11-07T17:39:45Z</dc:date>
    </item>
    <item>
      <title>Re: MMC standard tuning procedure does not work</title>
      <link>https://community.nxp.com/t5/S32G/MMC-standard-tuning-procedure-does-not-work/m-p/1368279#M219</link>
      <description>&lt;P&gt;Hi ttz766,&lt;/P&gt;
&lt;P&gt;I have tried your sequence, and it works.&lt;/P&gt;
&lt;P&gt;Thanks for your support!&lt;/P&gt;</description>
      <pubDate>Tue, 09 Nov 2021 07:10:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/MMC-standard-tuning-procedure-does-not-work/m-p/1368279#M219</guid>
      <dc:creator>thomaspham</dc:creator>
      <dc:date>2021-11-09T07:10:03Z</dc:date>
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