RX operation abnormality when connected via mac to mac RGMII

kdh — Tue, 17 Jan 2023 12:02:45 GMT

Hello~
I connected S32G2 and SWITCH (QCA8337N) through RGMII (MAC to MAC).
QCA8337 was set as MDC/MDIO and Ping was set to the PC connected to QCA.
It was confirmed that the ARP/ICMP request was normally transmitted to the PC and the ARP/ICMP response was transmitted to S32G2. (Check receipt with Wireshark on PC)
However, a ping fail occurred on S32G2.
S32G2 received the ARP response normally, but the next ICMP response is not being received.
However, when QCA mirrored the port connected to S32G2, the ICMP response was successfully delivered to S32G2.
Looking at the debug message below, the phrase "eqos_recv: RX packet not available" is repeatedly printed.
It is also confirmed that the ARP request coming from the PC after a certain period of time is well received and the ARP response is sent.
For reference, the [Rx_CRC_Error_Packets] register was 0.
What am I doing wrong?

------------------------------------------------------------------------------

Trying eth_eqos
eqos_start(dev=00000000fcd28bd0):
[[[[[[[[[[[[[[[[[[ 0x0
0x0 ]]]]]]]]]]]]]]]]]]
ofnode_read_u32_index: fsl,pins: 0x42 (66)
ofnode_read_u32_index: fsl,pins: 0x203001 (2109441)
ofnode_read_u32_index: fsl,pins: 0x43 (67)
ofnode_read_u32_index: fsl,pins: 0x200001 (2097153)
ofnode_read_u32_index: fsl,pins: 0x44 (68)
ofnode_read_u32_index: fsl,pins: 0x200001 (2097153)
ofnode_read_u32_index: fsl,pins: 0x45 (69)
ofnode_read_u32_index: fsl,pins: 0x200001 (2097153)
ofnode_read_u32_index: fsl,pins: 0x46 (70)
ofnode_read_u32_index: fsl,pins: 0x200001 (2097153)
ofnode_read_u32_index: fsl,pins: 0x47 (71)
ofnode_read_u32_index: fsl,pins: 0x200001 (2097153)
ofnode_read_u32_index: fsl,pins: 0x48 (72)
ofnode_read_u32_index: fsl,pins: 0x80000 (524288)
ofnode_read_u32_index: fsl,pins: 0x49 (73)
ofnode_read_u32_index: fsl,pins: 0x80000 (524288)
ofnode_read_u32_index: fsl,pins: 0x4a (74)
ofnode_read_u32_index: fsl,pins: 0x80000 (524288)
ofnode_read_u32_index: fsl,pins: 0x4b (75)
ofnode_read_u32_index: fsl,pins: 0x80000 (524288)
ofnode_read_u32_index: fsl,pins: 0x4c (76)
ofnode_read_u32_index: fsl,pins: 0x80000 (524288)
ofnode_read_u32_index: fsl,pins: 0x4d (77)
ofnode_read_u32_index: fsl,pins: 0x80000 (524288)
ofnode_read_u32_index: fsl,pins: 0x21a (538)
ofnode_read_u32_index: fsl,pins: 0x2 (2)
ofnode_read_u32_index: fsl,pins: 0x211 (529)
ofnode_read_u32_index: fsl,pins: 0x2 (2)
ofnode_read_u32_index: fsl,pins: 0x212 (530)
ofnode_read_u32_index: fsl,pins: 0x2 (2)
ofnode_read_u32_index: fsl,pins: 0x213 (531)
ofnode_read_u32_index: fsl,pins: 0x2 (2)
ofnode_read_u32_index: fsl,pins: 0x214 (532)
ofnode_read_u32_index: fsl,pins: 0x2 (2)
ofnode_read_u32_index: fsl,pins: 0x215 (533)
ofnode_read_u32_index: fsl,pins: 0x2 (2)
ofnode_read_u32_index: fsl,pins: 0x216 (534)
ofnode_read_u32_index: fsl,pins: 0x2 (2)
ofnode_read_u32_index: fsl,pins: 0x3c (60)
ofnode_read_u32_index: fsl,pins: 0x200001 (2097153)
ofnode_read_u32_index: fsl,pins: 0x3d (61)
ofnode_read_u32_index: fsl,pins: 0x280001 (2621441)
ofnode_read_u32_index: fsl,pins: 0x20f (527)
ofnode_read_u32_index: fsl,pins: 0x2 (2)
clk_get_by_name(dev=00000000fcd28bd0, name=tx_rgmii, clk=00000000fcd21578)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
clk_of_xlate_default(clk=00000000fcd21578)
clk_request(dev=00000000fcd28130, clk=00000000fcd21578)
clk_set_rate(clk=00000000fcd21578, rate=125000000)
clk_free(clk=00000000fcd21578)
clk_get_by_name(dev=00000000fcd28bd0, name=tx_rgmii, clk=00000000fcd21578)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
clk_of_xlate_default(clk=00000000fcd21578)
clk_request(dev=00000000fcd28130, clk=00000000fcd21578)
clk_enable(clk=00000000fcd21578)
clk_free(clk=00000000fcd21578)
clk_get_by_name(dev=00000000fcd28bd0, name=rx_rgmii, clk=00000000fcd215a8)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
clk_of_xlate_default(clk=00000000fcd215a8)
clk_request(dev=00000000fcd28130, clk=00000000fcd215a8)
clk_enable(clk=00000000fcd215a8)
clk_free(clk=00000000fcd215a8)
clk_get_by_name(dev=00000000fcd28bd0, name=tx_rgmii, clk=00000000fcd215a8)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
clk_of_xlate_default(clk=00000000fcd215a8)
clk_request(dev=00000000fcd28130, clk=00000000fcd215a8)
clk_enable(clk=00000000fcd215a8)
clk_free(clk=00000000fcd215a8)
clk_get_by_name(dev=00000000fcd28bd0, name=ts_rgmii, clk=00000000fcd215a8)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
clk_of_xlate_default(clk=00000000fcd215a8)
clk_request(dev=00000000fcd28130, clk=00000000fcd215a8)
clk_enable(clk=00000000fcd215a8)
clk_free(clk=00000000fcd215a8)
clk_get_by_name(dev=00000000fcd28bd0, name=axi, clk=00000000fcd215f8)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
clk_of_xlate_default(clk=00000000fcd215f8)
clk_request(dev=00000000fcd28130, clk=00000000fcd215f8)
clk_get_rate(clk=00000000fcd215f8)
clk_free(clk=00000000fcd215f8)
eqos_adjust_link(dev=00000000fcd28bd0):
eqos_set_full_duplex(dev=00000000fcd28bd0):
eqos_set_mii_speed_100(dev=00000000fcd28bd0):
clk_get_by_name(dev=00000000fcd28bd0, name=tx_rgmii, clk=00000000fcd215c8)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
clk_of_xlate_default(clk=00000000fcd215c8)
clk_request(dev=00000000fcd28130, clk=00000000fcd215c8)
clk_set_rate(clk=00000000fcd215c8, rate=25000000)
clk_free(clk=00000000fcd215c8)
clk_get_by_name(dev=00000000fcd28bd0, name=tx_rgmii, clk=00000000fcd215c8)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
fdtdec_get_int: #clock-cells: 0x1 (1)
clk_of_xlate_default(clk=00000000fcd215c8)
clk_request(dev=00000000fcd28130, clk=00000000fcd215c8)
clk_enable(clk=00000000fcd215c8)
clk_free(clk=00000000fcd215c8)
eqos_start: OK
Using eth_eqos device
eqos_send(dev=00000000fcd28bd0, packet=00000000fcfec880, length=42):

0xff 0xff 0xff 0xff 0xff 0xff 0x2 0x2d 0xc4 0x8 0xa0 0x8a 0x8 0x6 0x0 0x1
0x8 0x0 0x6 0x4 0x0 0x1 0x2 0x2d 0xc4 0x8 0xa0 0x8a 0xc0 0xa8 0x15 0x58
0x0 0x0 0x0 0x0 0x0 0x0 0xc0 0xa8 0x15 0xd2
eqos_recv(dev=00000000fcd28bd0, flags=1):
eqos_recv: *packetp=00000000fcd36980, length=60

0x2 0x2d 0xc4 0x8 0xa0 0x8a 0x7c 0xc2 0xc6 0x14 0x2b 0xad 0x8 0x6 0x0 0x1
0x8 0x0 0x6 0x4 0x0 0x2 0x7c 0xc2 0xc6 0x14 0x2b 0xad 0xc0 0xa8 0x15 0xd2
0x2 0x2d 0xc4 0x8 0xa0 0x8a 0xc0 0xa8 0x15 0x58 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
eqos_send(dev=00000000fcd28bd0, packet=00000000fcfed400, length=42):

0x7c 0xc2 0xc6 0x14 0x2b 0xad 0x2 0x2d 0xc4 0x8 0xa0 0x8a 0x8 0x0 0x45 0x0
0x0 0x1c 0x0 0x5 0x40 0x0 0xff 0x1 0xcf 0x60 0xc0 0xa8 0x15 0x58 0xc0 0xa8
0x15 0xd2 0x8 0x0 0xf7 0xfa 0x0 0x0 0x0 0x5
eqos_free_pkt(packet=00000000fcd36980, length=60)
eqos_recv(dev=00000000fcd28bd0, flags=0):
eqos_recv: RX packet not available
eqos_recv(dev=00000000fcd28bd0, flags=1):
eqos_recv: RX packet not available
eqos_recv(dev=00000000fcd28bd0, flags=1):
eqos_recv: RX packet not available
eqos_recv(dev=00000000fcd28bd0, flags=1):
eqos_recv: RX packet not available
eqos_recv(dev=00000000fcd28bd0, flags=1):
eqos_recv: RX packet not available

...

eqos_recv: RX packet not available
eqos_recv(dev=00000000fcd28bd0, flags=1):
eqos_recv: RX packet not available
eqos_recv(dev=00000000fcd28bd0, flags=1):
eqos_recv: *packetp=00000000fcd37600, length=60

0x2 0x2d 0xc4 0x8 0xa0 0x8a 0x7c 0xc2 0xc6 0x14 0x2b 0xad 0x8 0x6 0x0 0x1
0x8 0x0 0x6 0x4 0x0 0x1 0x7c 0xc2 0xc6 0x14 0x2b 0xad 0xc0 0xa8 0x15 0xd2
0x2 0x2d 0xc4 0x8 0xa0 0x8a 0xc0 0xa8 0x15 0x58 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
eqos_send(dev=00000000fcd28bd0, packet=00000000fcfed400, length=42):

0x7c 0xc2 0xc6 0x14 0x2b 0xad 0x2 0x2d 0xc4 0x8 0xa0 0x8a 0x8 0x6 0x0 0x1
0x8 0x0 0x6 0x4 0x0 0x2 0x2 0x2d 0xc4 0x8 0xa0 0x8a 0xc0 0xa8 0x15 0x58
0x7c 0xc2 0xc6 0x14 0x2b 0xad 0xc0 0xa8 0x15 0xd2
eqos_free_pkt(packet=00000000fcd37600, length=60)
eqos_recv(dev=00000000fcd28bd0, flags=0):
eqos_recv: RX packet not available
eqos_recv(dev=00000000fcd28bd0, flags=1):
eqos_recv: RX packet not available
eqos_recv(dev=00000000fcd28bd0, flags=1):
eqos_recv: RX packet not available

...

eqos_recv(dev=00000000fcd28bd0, flags=1):
eqos_recv: RX packet not available
eqos_recv(dev=00000000fcd28bd0, flags=1):
eqos_recv: RX packet not available
eqos_stop(dev=00000000fcd28bd0):
eqos_stop: OK
ping failed; host 192.168.21.210 is not alive
Command failed, result=1

Re: RX operation abnormality when connected via mac to mac RGMII

Daniel-Aguirre — Tue, 17 Jan 2023 18:04:19 GMT

Hi,

Could you provide which platform (if any) are you using for this application? Also, which drivers (RTD/BSP) are you using on the S32G side (IDE if any)?

Please, let us know.

Re: RX operation abnormality when connected via mac to mac RGMII

kdh — Wed, 18 Jan 2023 00:05:54 GMT

Hi~

I used S32g274ardb2 as the base platform and s32g_bsp28.0 version for bsp.
The interface used GMAC0 and set 100M (target is 1G) as fixed mode.

Thanks you.

Re: RX operation abnormality when connected via mac to mac RGMII

Daniel-Aguirre — Wed, 18 Jan 2023 18:35:02 GMT

Thanks for the information.

Have you tried updating to Linux BSP 33.0?? To see if the problem is related to version or to implementation.

Please, let us know.

topic Re: RX operation abnormality when connected via mac to mac RGMII in S32G

RX operation abnormality when connected via mac to mac RGMII

Re: RX operation abnormality when connected via mac to mac RGMII

Re: RX operation abnormality when connected via mac to mac RGMII

Re: RX operation abnormality when connected via mac to mac RGMII