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    <title>topic PTP over SJA1110 in S32G</title>
    <link>https://community.nxp.com/t5/S32G/PTP-over-SJA1110/m-p/2401785#M16713</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;We are debugging PTP on a PolarFire SoC GEM connected through an SJA1110 switch.&lt;/P&gt;&lt;P&gt;We observe that:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;PTP over Layer 2 (ptp4l -2) is received by the switch (ingress counters increase), but it is not forwarded (egress counters do not increase).&lt;/LI&gt;&lt;LI&gt;PTP over UDP (ptp4l ) is forwarded correctly through the same bridge path.&lt;/LI&gt;&lt;LI&gt;Normal Ethernet traffic (ICMP/ARP) also forwards correctly.&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;Is there any special handling or additional configuration required on the SJA1110 to forward Layer 2 PTP frames (destination MAC 01:1B:19:00:00:00) across bridged ports? Are there any known restrictions on forwarding Layer 2 PTP?&lt;/P&gt;&lt;P&gt;Also, is PTP over UDP (ptp4l) fully supported and recommended with the PolarFire SoC GEM, or is Layer 2 the only supported/recommended transport?&lt;/P&gt;&lt;P&gt;Any guidance would be appreciated.&lt;/P&gt;</description>
    <pubDate>Tue, 04 Aug 2026 09:53:37 GMT</pubDate>
    <dc:creator>Ankur_pixl</dc:creator>
    <dc:date>2026-08-04T09:53:37Z</dc:date>
    <item>
      <title>PTP over SJA1110</title>
      <link>https://community.nxp.com/t5/S32G/PTP-over-SJA1110/m-p/2401785#M16713</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;We are debugging PTP on a PolarFire SoC GEM connected through an SJA1110 switch.&lt;/P&gt;&lt;P&gt;We observe that:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;PTP over Layer 2 (ptp4l -2) is received by the switch (ingress counters increase), but it is not forwarded (egress counters do not increase).&lt;/LI&gt;&lt;LI&gt;PTP over UDP (ptp4l ) is forwarded correctly through the same bridge path.&lt;/LI&gt;&lt;LI&gt;Normal Ethernet traffic (ICMP/ARP) also forwards correctly.&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;Is there any special handling or additional configuration required on the SJA1110 to forward Layer 2 PTP frames (destination MAC 01:1B:19:00:00:00) across bridged ports? Are there any known restrictions on forwarding Layer 2 PTP?&lt;/P&gt;&lt;P&gt;Also, is PTP over UDP (ptp4l) fully supported and recommended with the PolarFire SoC GEM, or is Layer 2 the only supported/recommended transport?&lt;/P&gt;&lt;P&gt;Any guidance would be appreciated.&lt;/P&gt;</description>
      <pubDate>Tue, 04 Aug 2026 09:53:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/PTP-over-SJA1110/m-p/2401785#M16713</guid>
      <dc:creator>Ankur_pixl</dc:creator>
      <dc:date>2026-08-04T09:53:37Z</dc:date>
    </item>
    <item>
      <title>Re: PTP over SJA1110</title>
      <link>https://community.nxp.com/t5/S32G/PTP-over-SJA1110/m-p/2402145#M16717</link>
      <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/262906"&gt;@Ankur_pixl&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;DIV&gt;&lt;SPAN&gt;&lt;SPAN&gt;In a typical gPTP / time-aware bridge use case, the switch is not expected to forward all gPTP frames transparently as ordinary multicast traffic.&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN&gt;The usual flow is that the switch receives the gPTP frames from the Grandmaster, processes them through the gPTP stack running on the internal Cortex-M7 and then generates its own gPTP frames with the appropriate timestamps towards the connected downstream devices.&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;SJA1110 is typically configured for the Layer 2 Automotive Profile, where the PTP destination MAC address is 01:80:C2:00:00:0E. This address is used for 802.1AS/gPTP style Layer 2 transport and such frames are normally handled by the switch PTP/gPTP function rather than simply bridged as regular multicast traffic.&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;Your observation that the ingress counters increase, while the egress counters do not increase, suggests that the Layer 2 PTP frames are received by the switch but are not forwarded through the normal bridge path. One likely explanation is that the used PTP multicast MAC address is matched by the SJA1110 configuration, for example in the General Parameters table, DPI configuration, L2 Lookup Table or another PTP/trap-related configuration item, and the frames are therefore trapped to the host port, most likely to the internal Cortex-M7 host, instead of being forwarded to the expected external egress port.&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;This would also explain why PTP over UDP and normal Ethernet traffic such as ICMP/ARP are forwarded correctly. These frames do not match the same Layer 2 PTP/gPTP classification rule and are therefore handled as normal bridge traffic.&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;Please check the following points in your SJA1110 configuration:&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;1. Which PTP destination MAC address is configured in the switch, especially in the General Parameters table.&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;2. Whether PTP/gPTP frames are configured to be trapped to the host port.&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;3. Whether the internal Cortex-M7 host is running a gPTP stack or receiving the trapped PTP frames.&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;4. Whether the used destination MAC address is 01:1B:19:00:00:00 or 01:80:C2:00:00:0E.&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;5. Whether the L2 Lookup Table or multicast forwarding configuration contains an entry that forwards this destination MAC to the required external ports.&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;6. Whether the ingress and egress ports are in the same VLAN and forwarding domain for this traffic.&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;If your intention is to use SJA1110 as a gPTP/time-aware bridge, then the expected configuration is usually not simple transparent forwarding of the original gPTP frames. The switch should participate in the gPTP timing domain and generate the corresponding gPTP messages towards the connected devices.&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;If your intention is instead to use SJA1110 only as a plain Ethernet bridge for raw Layer 2 PTP frames, then the PTP trapping/special handling must be disabled or avoided for this traffic, and the corresponding multicast destination MAC address must be explicitly allowed in the L2 forwarding configuration.&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;Regarding the PolarFire SoC GEM, I cannot make a definitive statement about the recommended or fully supported PTP transport mode for that device. From the SJA1110 point of view, PTP over UDP may be forwarded as ordinary IP/UDP traffic if the bridge path allows it. However, this does not necessarily mean that UDP transport is supported or recommended by the PolarFire GEM driver for hardware timestamping. Please confirm the supported PTP transport and timestamping modes with the PolarFire SoC GEM documentation or with Microchip support.&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;P&gt;&lt;LI-WRAPPER&gt;&lt;/LI-WRAPPER&gt;&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Pavel&lt;/P&gt;</description>
      <pubDate>Wed, 05 Aug 2026 12:08:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/PTP-over-SJA1110/m-p/2402145#M16717</guid>
      <dc:creator>PavelL</dc:creator>
      <dc:date>2026-08-05T12:08:30Z</dc:date>
    </item>
    <item>
      <title>Re: PTP over SJA1110</title>
      <link>https://community.nxp.com/t5/S32G/PTP-over-SJA1110/m-p/2403247#M16729</link>
      <description>&lt;P class=""&gt;Hello,&lt;/P&gt;&lt;P class=""&gt;The destination MAC is 01:1B:19:00:00:00. We're using the switch with the Linux DSA bridge and have no control or configuration access over the Cortex-M7 core.&lt;/P&gt;&lt;P class=""&gt;How do we allow this traffic through in the L2 configuration? We used&amp;nbsp;bridge mdb, but it doesn't work; the entries install and even show as offloaded, yet the frames still aren't forwarded between the ports. Does this need to be set explicitly on the Cortex-M7 core?&lt;/P&gt;&lt;P class=""&gt;Additional context on our setup:&lt;/P&gt;&lt;P class=""&gt;Our MAC/port configuration is as follows:&lt;/P&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;PRE&gt;bridge mdb add dev br-EPS port epc2-uplink grp 01:1b:19:00:00:00 permanent
bridge mdb add dev br-EPS port t1-6        grp 01:1b:19:00:00:00 permanent&lt;/PRE&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;P class=""&gt;These show as offloaded in bridge -d mdb show, but L2 PTP frames arriving on one port are not forwarded out the other.&lt;/P&gt;&lt;P class=""&gt;Importantly, one of the switch ports does not have a working CPU port; it operates purely as a route between two ports (port-to-port forwarding), with no host/CPU port in that path. Since the reserved multicast 01:1b:19:00:00:00 appears to be trapped to the management/CPU route by default, and that route is not available here, we suspect the frames are being dropped rather than forwarded.&lt;/P&gt;&lt;P class=""&gt;Could you advise how to configure the switch to forward this reserved PTP multicast MAC in hardware between the two user ports, without relying on a CPU/management port?&lt;BR /&gt;&lt;BR /&gt;-- Ankur&lt;/P&gt;</description>
      <pubDate>Mon, 10 Aug 2026 09:29:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/PTP-over-SJA1110/m-p/2403247#M16729</guid>
      <dc:creator>Ankur_pixl</dc:creator>
      <dc:date>2026-08-10T09:29:32Z</dc:date>
    </item>
    <item>
      <title>Re: PTP over SJA1110</title>
      <link>https://community.nxp.com/t5/S32G/PTP-over-SJA1110/m-p/2403310#M16731</link>
      <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/262906"&gt;@Ankur_pixl&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;DIV&gt;&lt;SPAN&gt;The destination MAC address 01:1B:19:00:00:00 is an IEEE 1588 Layer 2 PTP multicast address. This is different from the 802.1AS / Automotive Profile gPTP destination MAC address 01:80:C2:00:00:0E, which is typically used in the SJA1110 gPTP Automotive Profile configuration.&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;Based on your description, this does not look like a standard Linux bridge MDB issue. The MDB entries may be correctly installed and even reported as offloaded, but the frame may still not reach the normal multicast forwarding path.&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;A likely explanation is that the SJA1110 hardware or the SJA1110 DSA driver classifies this destination MAC as a PTP/control frame before the normal L2 multicast forwarding decision is applied. In that case, the frame may be redirected to the CPU/management path instead of being forwarded directly between the two user ports.&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;This would explain the observed behavior:&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;- the ingress counter increases, so the frame is received by the switch,&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;- the MDB entries are installed and shown as offloaded,&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;- but the egress counter does not increase, because the frame is likely trapped to the CPU/management route before normal port-to-port forwarding is applied.&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;If the CPU/management route is not available in your port-to-port forwarding path, the trapped frame may effectively be dropped.&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;Regarding the Cortex-M7: if you are using the switch through the Linux DSA bridge and you do not run or control a gPTP stack on the internal Cortex-M7, then this should not normally be something configured from the Cortex-M7 application. In this use case, the relevant configuration is owned by the Linux DSA driver and by the switch hardware configuration programmed by that driver.&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;However, "bridge mdb" may not be sufficient if a dedicated PTP/control-frame trap rule is active for 01:1B:19:00:00:00. To forward this traffic directly in hardware between two user ports, the switch configuration would need to ensure that:&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;1. the PTP/control-frame trap for 01:1B:19:00:00:00 is disabled or bypassed for this traffic, and&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;2. a valid L2 multicast forwarding entry exists for 01:1B:19:00:00:00 towards the required user ports.&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;At this point, I would not expect the standard `bridge mdb` command alone to override a lower-level PTP/control-frame trap rule if such a rule is active in the SJA1110 DSA configuration.&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;As the next step, please check whether your SJA1110 DSA driver or BSP enables PTP hardware timestamping or installs any MAC filter / PTP trap rule for 01:1B:19:00:00:00. If such a rule is present, the solution will likely require a driver-level change or a switch static configuration change, rather than only a runtime Linux bridge MDB command.&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;Could you please share the following information?&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;- Linux BSP/kernel version,&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;- SJA1110 DSA driver source baseline,&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;- full output of "bridge -d mdb show",&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;- the involved DSA port names and physical switch port numbers,&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;- whether PTP hardware timestamping is enabled in the SJA1110 DSA driver,&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;- and, if possible, a packet capture on the DSA master/CPU interface to confirm whether the Layer 2 PTP frames are being trapped to the CPU path.&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;With this information we can further check whether the frames are being consumed by the PTP/control trap path, or whether there is another L2 multicast forwarding limitation.&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;P&gt;&lt;LI-WRAPPER&gt;&lt;/LI-WRAPPER&gt;&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Pavel&lt;/P&gt;</description>
      <pubDate>Mon, 10 Aug 2026 12:48:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/PTP-over-SJA1110/m-p/2403310#M16731</guid>
      <dc:creator>PavelL</dc:creator>
      <dc:date>2026-08-10T12:48:46Z</dc:date>
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