<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>S32GのトピックBest practice for time-deterministic (TAS) traffic when using LLCE + PFE CAN2ETH</title>
    <link>https://community.nxp.com/t5/S32G/Best-practice-for-time-deterministic-TAS-traffic-when-using-LLCE/m-p/2387410#M16493</link>
    <description>&lt;P&gt;Hello NXP Team,&lt;/P&gt;&lt;P&gt;We are working on a &lt;STRONG&gt;zonal architecture&lt;/STRONG&gt; using S32G399A&amp;nbsp;as Zone Controllers connected to HPC&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Current Architecture:&lt;/STRONG&gt;&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;We are currently using the GMAC with full Time-Aware Shaper (TAS / 802.1Qbv) support along with complete TSN features.&lt;/LI&gt;&lt;LI&gt;DDS runs over this GMAC path, and we have good time determinism for our service-oriented traffic.&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;STRONG&gt;New Exploration:&lt;/STRONG&gt;&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;We have successfully brought up and tested the official NXP LLCE + PFE sample application (CAN2ETH / ETH2CAN) as described in AN13423.&lt;/LI&gt;&lt;LI&gt;The goal is to offload selected high-frequency / low-latency CAN signals from ECUs directly via LLCE → PFE (IEEE1722 AVTP over UDP) to reduce CPU load and latency on the Zone Controller.&lt;/LI&gt;&lt;LI&gt;From community discussions, we understand that PFE only supports 802.1AS-Rev (time synchronization) and does not support Time-Aware Shaper (802.1Qbv / TAS) or Frame Preemption, unlike GMAC.&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;STRONG&gt;Question / Request for Guidance:&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;Since LLCE is tightly integrated with PFE (using PFE_HIF3), what is NXP’s recommended best practice in this scenario?&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;&lt;P&gt;Can we enable TAS support on PFE by using / customizing the PFE source code provided by NXP? (I saw that NXP provides PFE source code – would this help us add or enable TAS functionality?)&lt;/P&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;If TAS cannot be enabled on PFE, what is NXP’s recommended best practice to achieve strong time determinism for the LLCE + PFE CAN2ETH traffic?&lt;/P&gt;&lt;/LI&gt;&lt;LI&gt;Should critical time-sensitive CAN signals continue to use the GMAC + TAS path, while only non-critical or high-volume signals use LLCE + PFE?&lt;/LI&gt;&lt;LI&gt;Is the recommended approach to rely on an external TSN switch (such as SJA1110) downstream of the PFE port to provide full TAS scheduling for the tunneled traffic?&lt;/LI&gt;&lt;LI&gt;Are there any plans or firmware updates that will add TAS support on PFE in the future?&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;We want to decide the right split between GMAC and PFE paths without compromising determinism for safety-relevant or hard real-time signals.&lt;/P&gt;&lt;P&gt;Any official guidance, reference designs, or configuration recommendations would be very helpful.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you in advance!&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Arsal Imam&lt;/P&gt;&lt;P&gt;SDV Architect&amp;nbsp;@ &lt;SPAN&gt;GK&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN class=""&gt;Automobiltechnologie&lt;/SPAN&gt;&amp;nbsp;(Disrupt)&lt;/P&gt;</description>
    <pubDate>Sun, 28 Jun 2026 13:07:44 GMT</pubDate>
    <dc:creator>arsalimam</dc:creator>
    <dc:date>2026-06-28T13:07:44Z</dc:date>
    <item>
      <title>Best practice for time-deterministic (TAS) traffic when using LLCE + PFE CAN2ETH</title>
      <link>https://community.nxp.com/t5/S32G/Best-practice-for-time-deterministic-TAS-traffic-when-using-LLCE/m-p/2387410#M16493</link>
      <description>&lt;P&gt;Hello NXP Team,&lt;/P&gt;&lt;P&gt;We are working on a &lt;STRONG&gt;zonal architecture&lt;/STRONG&gt; using S32G399A&amp;nbsp;as Zone Controllers connected to HPC&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Current Architecture:&lt;/STRONG&gt;&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;We are currently using the GMAC with full Time-Aware Shaper (TAS / 802.1Qbv) support along with complete TSN features.&lt;/LI&gt;&lt;LI&gt;DDS runs over this GMAC path, and we have good time determinism for our service-oriented traffic.&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;STRONG&gt;New Exploration:&lt;/STRONG&gt;&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;We have successfully brought up and tested the official NXP LLCE + PFE sample application (CAN2ETH / ETH2CAN) as described in AN13423.&lt;/LI&gt;&lt;LI&gt;The goal is to offload selected high-frequency / low-latency CAN signals from ECUs directly via LLCE → PFE (IEEE1722 AVTP over UDP) to reduce CPU load and latency on the Zone Controller.&lt;/LI&gt;&lt;LI&gt;From community discussions, we understand that PFE only supports 802.1AS-Rev (time synchronization) and does not support Time-Aware Shaper (802.1Qbv / TAS) or Frame Preemption, unlike GMAC.&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;STRONG&gt;Question / Request for Guidance:&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;Since LLCE is tightly integrated with PFE (using PFE_HIF3), what is NXP’s recommended best practice in this scenario?&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;&lt;P&gt;Can we enable TAS support on PFE by using / customizing the PFE source code provided by NXP? (I saw that NXP provides PFE source code – would this help us add or enable TAS functionality?)&lt;/P&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;If TAS cannot be enabled on PFE, what is NXP’s recommended best practice to achieve strong time determinism for the LLCE + PFE CAN2ETH traffic?&lt;/P&gt;&lt;/LI&gt;&lt;LI&gt;Should critical time-sensitive CAN signals continue to use the GMAC + TAS path, while only non-critical or high-volume signals use LLCE + PFE?&lt;/LI&gt;&lt;LI&gt;Is the recommended approach to rely on an external TSN switch (such as SJA1110) downstream of the PFE port to provide full TAS scheduling for the tunneled traffic?&lt;/LI&gt;&lt;LI&gt;Are there any plans or firmware updates that will add TAS support on PFE in the future?&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;We want to decide the right split between GMAC and PFE paths without compromising determinism for safety-relevant or hard real-time signals.&lt;/P&gt;&lt;P&gt;Any official guidance, reference designs, or configuration recommendations would be very helpful.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you in advance!&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Arsal Imam&lt;/P&gt;&lt;P&gt;SDV Architect&amp;nbsp;@ &lt;SPAN&gt;GK&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN class=""&gt;Automobiltechnologie&lt;/SPAN&gt;&amp;nbsp;(Disrupt)&lt;/P&gt;</description>
      <pubDate>Sun, 28 Jun 2026 13:07:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Best-practice-for-time-deterministic-TAS-traffic-when-using-LLCE/m-p/2387410#M16493</guid>
      <dc:creator>arsalimam</dc:creator>
      <dc:date>2026-06-28T13:07:44Z</dc:date>
    </item>
    <item>
      <title>Re: Best practice for time-deterministic (TAS) traffic when using LLCE + PFE CAN2ETH</title>
      <link>https://community.nxp.com/t5/S32G/Best-practice-for-time-deterministic-TAS-traffic-when-using-LLCE/m-p/2387432#M16494</link>
      <description>&lt;P&gt;Hi,&lt;SPAN&gt;arsalimam&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;Thank you for your contacting and detail information.&lt;/P&gt;
&lt;P&gt;I have received your questions and will help you to check it.&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Joey&lt;/P&gt;</description>
      <pubDate>Mon, 29 Jun 2026 02:06:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Best-practice-for-time-deterministic-TAS-traffic-when-using-LLCE/m-p/2387432#M16494</guid>
      <dc:creator>Joey_z</dc:creator>
      <dc:date>2026-06-29T02:06:40Z</dc:date>
    </item>
  </channel>
</rss>

