<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: S32G3 DDR size change in S32G</title>
    <link>https://community.nxp.com/t5/S32G/S32G3-DDR-size-change/m-p/2377485#M16419</link>
    <description>&lt;P&gt;Hello,&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/263449"&gt;@FlaviuNistor&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks for your reply.&lt;/P&gt;
&lt;P&gt;1. Sorry that I do not have such files for EVB, you may try generating them via DDR tools with your EVB.&lt;/P&gt;
&lt;P&gt;2. Let me summarize the possible steps:&lt;/P&gt;
&lt;P&gt;a. Connect your custom board with PC, and run ddr tools to generate corresponding files&lt;/P&gt;
&lt;P&gt;b. Once generated, copy all the files generated to&amp;nbsp; your TFA code base.&lt;/P&gt;
&lt;P&gt;c. Try building it with&amp;nbsp;&lt;SPAN&gt;CUSTOM_DDR_DRV=$(Generated_Code)&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;3. There may also be modifications needed for U-boot to run the BSP code correctly on your custom board.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;BR&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Chenyin&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Fri, 05 Jun 2026 10:08:45 GMT</pubDate>
    <dc:creator>chenyin_h</dc:creator>
    <dc:date>2026-06-05T10:08:45Z</dc:date>
    <item>
      <title>S32G3 DDR size change</title>
      <link>https://community.nxp.com/t5/S32G/S32G3-DDR-size-change/m-p/2376582#M16406</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I need to change to DDR size from the default 4G to 2G for a custom ECU using S32g3. For BSP 46.00 I know this is part of the BL2 (TFA) and there a is chapter in the BSP user manual, BUT...&lt;/P&gt;&lt;P&gt;the steps described there are "manual", meaning the TFA should be build as an independent binary.&lt;/P&gt;&lt;P&gt;I am using Yocto with BSP46.00 and took as a start reference&amp;nbsp;s32g399aevb3. I have created my own custom MACHINE and meta layer and can successfully do the bitbake and run the image on the EVB (still 4G as original MACHINE).&lt;/P&gt;&lt;P&gt;Now I want to integrate the DDR size change (4G -&amp;gt; 2G) in my Yocto flow. For now I am thinking to add the new ddr files as a patch in a bbapend for TFA recipe, but the issue is that Yocto build will fail if&amp;nbsp;NXP_FIRMWARE_LOCAL_DIR is not provided.&lt;/P&gt;&lt;P&gt;My questions are:&lt;/P&gt;&lt;P&gt;1. Is the "manual" option the only one (I hope not)?&lt;/P&gt;&lt;P&gt;2. Is my intended approach correct?&lt;/P&gt;&lt;P&gt;3. If using a patch for TFA (or even pointing to a local repo) in the bbapend, how can I avoid the build fail caused by removing&amp;nbsp;NXP_FIRMWARE_LOCAL_DIR? I expect that I can't create my own binaries and also makes no sense to have my changes for ddr and also the ddr_firmware intended for the EVB (that is why I need to remove NXP_FIRMWARE_LOCAL_DIR).&lt;/P&gt;</description>
      <pubDate>Thu, 04 Jun 2026 08:02:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G3-DDR-size-change/m-p/2376582#M16406</guid>
      <dc:creator>FlaviuNistor</dc:creator>
      <dc:date>2026-06-04T08:02:23Z</dc:date>
    </item>
    <item>
      <title>Re: S32G3 DDR size change</title>
      <link>https://community.nxp.com/t5/S32G/S32G3-DDR-size-change/m-p/2376767#M16411</link>
      <description>&lt;P&gt;Hello,&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/263449"&gt;@FlaviuNistor&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks for your post.&lt;/P&gt;
&lt;P&gt;1.&amp;nbsp;The DDR_FW_BIN_PATH parameter must be set to specify the path to the&lt;STRONG&gt; NXP board-specific DDR firmware binary&lt;/STRONG&gt; file, so it is only for building images for NXP board(RDB, EVB, etc.)&lt;/P&gt;
&lt;P&gt;2. For building TFA for custom board, it is suggested using the&amp;nbsp; &lt;SPAN class="fontstyle2"&gt;CUSTOM_DDR_DRV &lt;/SPAN&gt;&lt;SPAN class="fontstyle0"&gt;parameter for &lt;/SPAN&gt;&lt;SPAN class="fontstyle2"&gt;make&lt;/SPAN&gt;&lt;SPAN class="fontstyle0"&gt;. It must be set to a path (relative to the TF-A root folder) where all the DDR source and header files are, in the state they were generated by DDR Tool.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;3. Once the TFA could be build correctly, you may make the changes to the Yocto accordingly to have further test.&lt;/P&gt;
&lt;P&gt;I hope it will help.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Chenyin&lt;/P&gt;</description>
      <pubDate>Thu, 04 Jun 2026 10:14:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G3-DDR-size-change/m-p/2376767#M16411</guid>
      <dc:creator>chenyin_h</dc:creator>
      <dc:date>2026-06-04T10:14:32Z</dc:date>
    </item>
    <item>
      <title>Re: S32G3 DDR size change</title>
      <link>https://community.nxp.com/t5/S32G/S32G3-DDR-size-change/m-p/2377471#M16418</link>
      <description>Hello Chenyin,&lt;BR /&gt;&lt;BR /&gt;1. This is clear now.&lt;BR /&gt;2. Since I do not have yet some generated custom files, can you please provide the needed files for the NXP EVB board (S32G-VNP-EVB) so I can test my build flow?&lt;BR /&gt;3. A bbappend for arm-trusted-firmware containing: EXTRA_OEMAKE:append:s32g = " CUSTOM_DDR_DRV=$(realpath --relative-to=${S} $(pwd)/../../../../../../../linuxbsp_ddr_config)" should be the right solution.&lt;BR /&gt;&lt;BR /&gt;As a new question:&lt;BR /&gt;4. If I have to change the DDR size, do I have to also modify something in U-boot or is the TFA change enough?</description>
      <pubDate>Fri, 05 Jun 2026 09:42:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G3-DDR-size-change/m-p/2377471#M16418</guid>
      <dc:creator>FlaviuNistor</dc:creator>
      <dc:date>2026-06-05T09:42:51Z</dc:date>
    </item>
    <item>
      <title>Re: S32G3 DDR size change</title>
      <link>https://community.nxp.com/t5/S32G/S32G3-DDR-size-change/m-p/2377485#M16419</link>
      <description>&lt;P&gt;Hello,&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/263449"&gt;@FlaviuNistor&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks for your reply.&lt;/P&gt;
&lt;P&gt;1. Sorry that I do not have such files for EVB, you may try generating them via DDR tools with your EVB.&lt;/P&gt;
&lt;P&gt;2. Let me summarize the possible steps:&lt;/P&gt;
&lt;P&gt;a. Connect your custom board with PC, and run ddr tools to generate corresponding files&lt;/P&gt;
&lt;P&gt;b. Once generated, copy all the files generated to&amp;nbsp; your TFA code base.&lt;/P&gt;
&lt;P&gt;c. Try building it with&amp;nbsp;&lt;SPAN&gt;CUSTOM_DDR_DRV=$(Generated_Code)&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;3. There may also be modifications needed for U-boot to run the BSP code correctly on your custom board.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;BR&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Chenyin&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 05 Jun 2026 10:08:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G3-DDR-size-change/m-p/2377485#M16419</guid>
      <dc:creator>chenyin_h</dc:creator>
      <dc:date>2026-06-05T10:08:45Z</dc:date>
    </item>
  </channel>
</rss>

