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    <title>topic s32g_LLCE in S32G</title>
    <link>https://community.nxp.com/t5/S32G/s32g-LLCE/m-p/2331069#M16103</link>
    <description>&lt;P&gt;I should like to ask about the LLCE module in the S32 series. Taking the example of forwarding CAN frames to Ethernet or Ethernet frames to CAN frames, does its routing and forwarding behaviour rely entirely on hardware lookup tables to map to the destination? Or does it require the CPU to read data from the corresponding cache area, then perform a software lookup to store it in system RAM, before the CPU writes it to the destination? Could you outline the process? Hardware-based routing would be considerably faster but less flexible, whereas software routing would take significantly longer. The documentation only mentions the firmware module without detailing the specific operations involved.&lt;/P&gt;</description>
    <pubDate>Thu, 12 Mar 2026 06:07:31 GMT</pubDate>
    <dc:creator>yuancz</dc:creator>
    <dc:date>2026-03-12T06:07:31Z</dc:date>
    <item>
      <title>s32g_LLCE</title>
      <link>https://community.nxp.com/t5/S32G/s32g-LLCE/m-p/2331069#M16103</link>
      <description>&lt;P&gt;I should like to ask about the LLCE module in the S32 series. Taking the example of forwarding CAN frames to Ethernet or Ethernet frames to CAN frames, does its routing and forwarding behaviour rely entirely on hardware lookup tables to map to the destination? Or does it require the CPU to read data from the corresponding cache area, then perform a software lookup to store it in system RAM, before the CPU writes it to the destination? Could you outline the process? Hardware-based routing would be considerably faster but less flexible, whereas software routing would take significantly longer. The documentation only mentions the firmware module without detailing the specific operations involved.&lt;/P&gt;</description>
      <pubDate>Thu, 12 Mar 2026 06:07:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/s32g-LLCE/m-p/2331069#M16103</guid>
      <dc:creator>yuancz</dc:creator>
      <dc:date>2026-03-12T06:07:31Z</dc:date>
    </item>
    <item>
      <title>Re: s32g_LLCE</title>
      <link>https://community.nxp.com/t5/S32G/s32g-LLCE/m-p/2331158#M16105</link>
      <description>&lt;P&gt;Hello,&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/260398"&gt;@yuancz&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks for your post.&lt;/P&gt;
&lt;P&gt;Take ETH2CAN for example, no intervention between the CPU cores of S32G and LLCE/PFE when routing ethernet frames to CAN.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="1.png" style="width: 404px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/379054i0389B00D428F0F6B/image-size/large?v=v2&amp;amp;px=999" role="button" title="1.png" alt="1.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Chenyin&lt;/P&gt;</description>
      <pubDate>Thu, 12 Mar 2026 08:34:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/s32g-LLCE/m-p/2331158#M16105</guid>
      <dc:creator>chenyin_h</dc:creator>
      <dc:date>2026-03-12T08:34:42Z</dc:date>
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